Re: [PATCH for-6.2 24/34] target/arm: Implement MVE VMLADAV and VMLSLDAV

2021-07-21 Thread Richard Henderson 

On 7/13/21 3:37 AM, Peter Maydell wrote:

Implement the MVE VMLADAV and VMLSLDAV insns.  Like the VMLALDAV and
VMLSLDAV insns already implemented, these accumulate multiplied
vector elements; but they accumulate a 32-bit result rather than a
64-bit one.

Note that these encodings overlap with what would be RdaHi=0b111 for
VMLALDAV, VMLSLDAV, VRMLALDAVH and VRMLSLDAVH.

Signed-off-by: Peter Maydell
---
  target/arm/helper-mve.h| 17 ++
  target/arm/mve.decode  | 33 +---
  target/arm/mve_helper.c| 41 
  target/arm/translate-mve.c | 64 ++
  4 files changed, 150 insertions(+), 5 deletions(-)


Reviewed-by: Richard Henderson 

r~

[PATCH for-6.2 24/34] target/arm: Implement MVE VMLADAV and VMLSLDAV

2021-07-13 Thread Peter Maydell 
Implement the MVE VMLADAV and VMLSLDAV insns.  Like the VMLALDAV and
VMLSLDAV insns already implemented, these accumulate multiplied
vector elements; but they accumulate a 32-bit result rather than a
64-bit one.

Note that these encodings overlap with what would be RdaHi=0b111 for
VMLALDAV, VMLSLDAV, VRMLALDAVH and VRMLSLDAVH.

Signed-off-by: Peter Maydell 
---
 target/arm/helper-mve.h| 17 ++
 target/arm/mve.decode  | 33 +---
 target/arm/mve_helper.c| 41 
 target/arm/translate-mve.c | 64 ++
 4 files changed, 150 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 84aa9de6e06..088bdd3ca50 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -400,6 +400,23 @@ DEF_HELPER_FLAGS_4(mve_vrmlaldavhuw, TCG_CALL_NO_WG, i64, 
env, ptr, ptr, i64)
 DEF_HELPER_FLAGS_4(mve_vrmlsldavhsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
 DEF_HELPER_FLAGS_4(mve_vrmlsldavhxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
 
+DEF_HELPER_FLAGS_4(mve_vmladavsb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmladavsh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmladavsw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmladavub, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmladavuh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmladavuw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmlsdavb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmlsdavh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmlsdavw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vmladavsxb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmladavsxh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmladavsxw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmlsdavxb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmlsdavxh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmlsdavxw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
+
 DEF_HELPER_FLAGS_3(mve_vaddvsb, TCG_CALL_NO_WG, i32, env, ptr, i32)
 DEF_HELPER_FLAGS_3(mve_vaddvub, TCG_CALL_NO_WG, i32, env, ptr, i32)
 DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 79c529e762f..0c4708ea988 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -320,32 +320,55 @@ VDUP 1110 1110 1 0 10 ... 0  1011 . 0 0 1 
 @vdup size=2
 %size_16 16:1 !function=plus_1
 
  rdahi rdalo size qn qm x a
+ rda size qn qm x a
 
 @vmlaldav  . ... ... . ... x:1  .. a:1 . qm:3 . \
  qn=%qn rdahi=%rdahi rdalo=%rdalo size=%size_16 
 @vmlaldav_nosz     . ... ... . ... x:1  .. a:1 . qm:3 . \
  qn=%qn rdahi=%rdahi rdalo=%rdalo size=0 
-VMLALDAV_S   1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav
-VMLALDAV_U    1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav
+@vmladav    ... . ... x:1  . . a:1 . qm:3 . \
+ qn=%qn rda=%rdalo size=%size_16 
+@vmladav_nosz   ... . ... x:1  . . a:1 . qm:3 . \
+ qn=%qn rda=%rdalo size=0 
 
-VMLSLDAV 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 1 @vmlaldav
+{
+  VMLADAV_S  1110 1110   ... . ... . 1110 . 0 . 0 ... 0 @vmladav
+  VMLALDAV_S 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav
+}
+{
+  VMLADAV_U   1110   ... . ... . 1110 . 0 . 0 ... 0 @vmladav
+  VMLALDAV_U  1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav
+}
+
+{
+  VMLSDAV1110 1110   ... . ... . 1110 . 0 . 0 ... 1 @vmladav
+  VMLSLDAV   1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 1 @vmlaldav
+}
+
+{
+  VMLSDAV 1110   ... 0 ... . 1110 . 0 . 0 ... 1 @vmladav_nosz
+  VRMLSLDAVH  1110 1 ... ... 0 ... . 1110 . 0 . 0 ... 1 @vmlaldav_nosz
+}
+
+VMLADAV_S1110 1110   ... 0 ... .  . 0 . 0 ... 1 @vmladav_nosz
+VMLADAV_U 1110   ... 0 ... .  . 0 . 0 ... 1 @vmladav_nosz
 
 {
   VMAXV_S1110 1110 1110  .. 10    0 0 . 0 ... 0 @vmaxv
   VMINV_S1110 1110 1110  .. 10    1 0 . 0 ... 0 @vmaxv
   VMAXAV 1110 1110 1110  .. 00    0 0 . 0 ... 0 @vmaxv
   VMINAV 1110 1110 1110  .. 00    1 0 . 0 ... 0 @vmaxv
+  VMLADAV_S  1110 1110   ... 0 ... .  . 0 . 0 ... 0 @vmladav_nosz
   VRMLALDAVH_S   1110 1110 1 ... ... 0 ... .  . 0 . 0 ... 0 @vmlaldav_nosz
 }
 
 {
   VMAXV_U 1110 1110  .. 10    0 0 . 0 ... 0 @vmaxv
   VMINV_U 1110 1110  .. 10    1 0 . 0 ... 0 @vmaxv
+  VMLADAV_U   1110   ... 0 ... .  . 0 . 0 ... 0 @vmladav_nosz
   VRMLALDAVH_U    1110 1 ...