[PATCH v0 1/2] hw/riscv/opentitan: bump opentitan
From: Wilfred Mallawa This patch updates the OpenTitan model to match the specified register layout as per [1]. Which is also the latest commit of OpenTitan supported by TockOS. Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes any references to Padctrl. Note: OpenTitan doc [2] has not yet specified much detail regarding this, except for a note that states `TODO: this section needs to be updated to reflect the pinmux/padctrl merger` [1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/ [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview Signed-off-by: Wilfred Mallawa --- hw/riscv/opentitan.c | 13 + include/hw/riscv/opentitan.h | 9 - 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index be7ff1eea0..373fed36b6 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -29,7 +29,7 @@ #include "sysemu/sysemu.h" static const MemMapEntry ibex_memmap[] = { -[IBEX_DEV_ROM] ={ 0x8000, 0x8000 }, +[IBEX_DEV_ROM] ={ 0x8000, 0x8000 }, [IBEX_DEV_RAM] ={ 0x1000, 0x2 }, [IBEX_DEV_FLASH] = { 0x2000, 0x10 }, [IBEX_DEV_UART] = { 0x4000, 0x1000 }, @@ -38,17 +38,17 @@ static const MemMapEntry ibex_memmap[] = { [IBEX_DEV_I2C] ={ 0x4008, 0x1000 }, [IBEX_DEV_PATTGEN] ={ 0x400e, 0x1000 }, [IBEX_DEV_TIMER] = { 0x4010, 0x1000 }, -[IBEX_DEV_SENSOR_CTRL] ={ 0x4011, 0x1000 }, [IBEX_DEV_OTP_CTRL] = { 0x4013, 0x4000 }, [IBEX_DEV_LC_CTRL] ={ 0x4014, 0x1000 }, -[IBEX_DEV_USBDEV] = { 0x4015, 0x1000 }, +[IBEX_DEV_ALERT_HANDLER] = { 0x4015, 0x1000 }, [IBEX_DEV_SPI_HOST0] = { 0x4030, 0x1000 }, [IBEX_DEV_SPI_HOST1] = { 0x4031, 0x1000 }, +[IBEX_DEV_USBDEV] = { 0x4032, 0x1000 }, [IBEX_DEV_PWRMGR] = { 0x4040, 0x1000 }, [IBEX_DEV_RSTMGR] = { 0x4041, 0x1000 }, [IBEX_DEV_CLKMGR] = { 0x4042, 0x1000 }, [IBEX_DEV_PINMUX] = { 0x4046, 0x1000 }, -[IBEX_DEV_PADCTRL] ={ 0x4047, 0x1000 }, +[IBEX_DEV_SENSOR_CTRL] ={ 0x4049, 0x1000 }, [IBEX_DEV_FLASH_CTRL] = { 0x4100, 0x1000 }, [IBEX_DEV_AES] ={ 0x4110, 0x1000 }, [IBEX_DEV_HMAC] = { 0x4111, 0x1000 }, @@ -59,10 +59,9 @@ static const MemMapEntry ibex_memmap[] = { [IBEX_DEV_ENTROPY] ={ 0x4116, 0x1000 }, [IBEX_DEV_EDNO] = { 0x4117, 0x1000 }, [IBEX_DEV_EDN1] = { 0x4118, 0x1000 }, -[IBEX_DEV_ALERT_HANDLER] = { 0x411b, 0x1000 }, [IBEX_DEV_NMI_GEN] ={ 0x411c, 0x1000 }, [IBEX_DEV_PERI] = { 0x411f, 0x1 }, -[IBEX_DEV_PLIC] = { 0x4800, 0x4005000 }, +[IBEX_DEV_PLIC] = { 0x4800, 0x4005000 }, [IBEX_DEV_FLASH_VIRTUAL] = { 0x8000, 0x8 }, }; @@ -265,8 +264,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); create_unimplemented_device("riscv.lowrisc.ibex.pinmux", memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); -create_unimplemented_device("riscv.lowrisc.ibex.padctrl", -memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size); create_unimplemented_device("riscv.lowrisc.ibex.usbdev", memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 6665cd5794..1fc055cdff 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -81,7 +81,6 @@ enum { IBEX_DEV_RSTMGR, IBEX_DEV_CLKMGR, IBEX_DEV_PINMUX, -IBEX_DEV_PADCTRL, IBEX_DEV_USBDEV, IBEX_DEV_FLASH_CTRL, IBEX_DEV_PLIC, @@ -109,10 +108,10 @@ enum { IBEX_UART0_RX_TIMEOUT_IRQ = 7, IBEX_UART0_RX_PARITY_ERR_IRQ = 8, IBEX_TIMER_TIMEREXPIRED0_0= 127, -IBEX_SPI_HOST0_ERR_IRQ= 151, -IBEX_SPI_HOST0_SPI_EVENT_IRQ = 152, -IBEX_SPI_HOST1_ERR_IRQ= 153, -IBEX_SPI_HOST1_SPI_EVENT_IRQ = 154, +IBEX_SPI_HOST0_ERR_IRQ= 134, +IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135, +IBEX_SPI_HOST1_ERR_IRQ= 136, +IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137, }; #endif -- 2.37.3
Re: [PATCH v0 1/2] hw/riscv/opentitan: bump opentitan
On Tue, Oct 25, 2022 at 9:17 AM Wilfred Mallawa wrote: > > From: Wilfred Mallawa > > This patch updates the OpenTitan model to match > the specified register layout as per [1]. Which is also the latest > commit of OpenTitan supported by TockOS. > > Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch > removes > any references to Padctrl. Note: OpenTitan doc [2] has not yet specified > much detail regarding this, except for a note that states `TODO: this > section needs to be updated to reflect the pinmux/padctrl merger` > > [1] > https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h > [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/ > [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview > > Signed-off-by: Wilfred Mallawa > --- > hw/riscv/opentitan.c | 13 + > include/hw/riscv/opentitan.h | 9 - > 2 files changed, 9 insertions(+), 13 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v0 1/2] hw/riscv/opentitan: bump opentitan
On Tue, Oct 25, 2022 at 11:18 AM Wilfred Mallawa wrote: > > From: Wilfred Mallawa > > This patch updates the OpenTitan model to match > the specified register layout as per [1]. Which is also the latest > commit of OpenTitan supported by TockOS. > > Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch > removes > any references to Padctrl. Note: OpenTitan doc [2] has not yet specified > much detail regarding this, except for a note that states `TODO: this > section needs to be updated to reflect the pinmux/padctrl merger` > > [1] > https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h > [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/ > [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview > > Signed-off-by: Wilfred Mallawa Can you add a comment to the OpenTitan machine in QEMU specifying what git SHA of OT we are targeting? Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/opentitan.c | 13 + > include/hw/riscv/opentitan.h | 9 - > 2 files changed, 9 insertions(+), 13 deletions(-) > > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index be7ff1eea0..373fed36b6 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -29,7 +29,7 @@ > #include "sysemu/sysemu.h" > > static const MemMapEntry ibex_memmap[] = { > -[IBEX_DEV_ROM] ={ 0x8000, 0x8000 }, > +[IBEX_DEV_ROM] ={ 0x8000, 0x8000 }, > [IBEX_DEV_RAM] ={ 0x1000, 0x2 }, > [IBEX_DEV_FLASH] = { 0x2000, 0x10 }, > [IBEX_DEV_UART] = { 0x4000, 0x1000 }, > @@ -38,17 +38,17 @@ static const MemMapEntry ibex_memmap[] = { > [IBEX_DEV_I2C] ={ 0x4008, 0x1000 }, > [IBEX_DEV_PATTGEN] ={ 0x400e, 0x1000 }, > [IBEX_DEV_TIMER] = { 0x4010, 0x1000 }, > -[IBEX_DEV_SENSOR_CTRL] ={ 0x4011, 0x1000 }, > [IBEX_DEV_OTP_CTRL] = { 0x4013, 0x4000 }, > [IBEX_DEV_LC_CTRL] ={ 0x4014, 0x1000 }, > -[IBEX_DEV_USBDEV] = { 0x4015, 0x1000 }, > +[IBEX_DEV_ALERT_HANDLER] = { 0x4015, 0x1000 }, > [IBEX_DEV_SPI_HOST0] = { 0x4030, 0x1000 }, > [IBEX_DEV_SPI_HOST1] = { 0x4031, 0x1000 }, > +[IBEX_DEV_USBDEV] = { 0x4032, 0x1000 }, > [IBEX_DEV_PWRMGR] = { 0x4040, 0x1000 }, > [IBEX_DEV_RSTMGR] = { 0x4041, 0x1000 }, > [IBEX_DEV_CLKMGR] = { 0x4042, 0x1000 }, > [IBEX_DEV_PINMUX] = { 0x4046, 0x1000 }, > -[IBEX_DEV_PADCTRL] ={ 0x4047, 0x1000 }, > +[IBEX_DEV_SENSOR_CTRL] ={ 0x4049, 0x1000 }, > [IBEX_DEV_FLASH_CTRL] = { 0x4100, 0x1000 }, > [IBEX_DEV_AES] ={ 0x4110, 0x1000 }, > [IBEX_DEV_HMAC] = { 0x4111, 0x1000 }, > @@ -59,10 +59,9 @@ static const MemMapEntry ibex_memmap[] = { > [IBEX_DEV_ENTROPY] ={ 0x4116, 0x1000 }, > [IBEX_DEV_EDNO] = { 0x4117, 0x1000 }, > [IBEX_DEV_EDN1] = { 0x4118, 0x1000 }, > -[IBEX_DEV_ALERT_HANDLER] = { 0x411b, 0x1000 }, > [IBEX_DEV_NMI_GEN] ={ 0x411c, 0x1000 }, > [IBEX_DEV_PERI] = { 0x411f, 0x1 }, > -[IBEX_DEV_PLIC] = { 0x4800, 0x4005000 }, > +[IBEX_DEV_PLIC] = { 0x4800, 0x4005000 }, > [IBEX_DEV_FLASH_VIRTUAL] = { 0x8000, 0x8 }, > }; > > @@ -265,8 +264,6 @@ static void lowrisc_ibex_soc_realize(DeviceState > *dev_soc, Error **errp) > memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); > create_unimplemented_device("riscv.lowrisc.ibex.pinmux", > memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); > -create_unimplemented_device("riscv.lowrisc.ibex.padctrl", > -memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size); > create_unimplemented_device("riscv.lowrisc.ibex.usbdev", > memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); > create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", > diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h > index 6665cd5794..1fc055cdff 100644 > --- a/include/hw/riscv/opentitan.h > +++ b/include/hw/riscv/opentitan.h > @@ -81,7 +81,6 @@ enum { > IBEX_DEV_RSTMGR, > IBEX_DEV_CLKMGR, > IBEX_DEV_PINMUX, > -IBEX_DEV_PADCTRL, > IBEX_DEV_USBDEV, > IBEX_DEV_FLASH_CTRL, > IBEX_DEV_PLIC, > @@ -109,10 +108,10 @@ enum { > IBEX_UART0_RX_TIMEOUT_IRQ = 7, > IBEX_UART0_RX_PARITY_ERR_IRQ = 8, > IBEX_TIMER_TIMEREXPIRED0_0= 127, > -IBEX_SPI_HOST0_ERR_IRQ= 151, > -IBEX_SPI_HOST0_SPI_EVENT_IRQ = 152, > -IBEX_SPI_HOST1_ERR_IRQ= 153, > -IBEX_SPI