Re: [PATCH v1 1/2] hw/misc: add ibex lifecycle controller
On Wed, Sep 28, 2022 at 3:11 PM Wilfred Mallawa wrote: > > From: Wilfred Mallawa > > Device model for the OpenTitan lifecycle controller as per [1]. > > Addition of this model is the first of many steps to adding `boot_rom` > support for OpenTitan. The OpenTitan `boot_rom` needs to access the > lifecycle controller during the init/test sequence before it jumps to > flash. With this model, we can get past the lifecycle controller stages > in boot. > > Currently the supported functionality is limited. > > [1] https://docs.opentitan.org/hw/ip/lc_ctrl/doc/ > > Signed-off-by: Wilfred Mallawa > --- > hw/misc/ibex_lc_ctrl.c | 287 + > hw/misc/meson.build| 3 + > hw/misc/trace-events | 5 + > include/hw/misc/ibex_lc_ctrl.h | 121 ++ > 4 files changed, 416 insertions(+) > create mode 100644 hw/misc/ibex_lc_ctrl.c > create mode 100644 include/hw/misc/ibex_lc_ctrl.h > > diff --git a/hw/misc/ibex_lc_ctrl.c b/hw/misc/ibex_lc_ctrl.c > new file mode 100644 > index 00..f034a92a9c > --- /dev/null > +++ b/hw/misc/ibex_lc_ctrl.c > @@ -0,0 +1,287 @@ > +/* > + * QEMU model of the Ibex Life Cycle Controller > + * SPEC Reference: https://docs.opentitan.org/hw/ip/lc_ctrl/doc/ > + * > + * Copyright (C) 2022 Western Digital > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > copy > + * of this software and associated documentation files (the "Software"), to > deal > + * in the Software without restriction, including without limitation the > rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "qemu/module.h" > +#include "hw/misc/ibex_lc_ctrl.h" > +#include "hw/irq.h" > +#include "hw/qdev-properties.h" > +#include "hw/qdev-properties-system.h" > +#include "migration/vmstate.h" > +#include "trace.h" > + > +REG32(ALERT_TEST, 0x00) > +FIELD(ALERT_TEST, FETAL_PROG_ERR, 0, 1) > +FIELD(ALERT_TEST, FETAL_STATE_ERR, 1, 1) > +FIELD(ALERT_TEST, FETAL_BUS_INTEG_ERR, 2, 1) > +REG32(CTRL_STATUS, 0x04) > +FIELD(CTRL_STATUS, READY, 0, 1) > +FIELD(CTRL_STATUS, TRANSITION_SUCCESSFUL, 0, 1) > +FIELD(CTRL_STATUS, TRANSITION_COUNT_ERROR, 1, 1) > +FIELD(CTRL_STATUS, TRANSITION_ERROR, 2, 1) > +FIELD(CTRL_STATUS, TOKEN_ERROR, 3, 1) > +FIELD(CTRL_STATUS, FLASH_RMA_ERROR, 4, 1) > +FIELD(CTRL_STATUS, OTP_ERROR, 5, 1) > +FIELD(CTRL_STATUS, STATE_ERROR, 6, 1) > +FIELD(CTRL_STATUS, BUS_INTEG_ERROR, 7, 1) > +FIELD(CTRL_STATUS, OTP_PARTITION_ERROR, 8, 1) > +REG32(CLAIM_TRANSITION_IF, 0x08) > + FIELD(CLAIM_TRANSITION_IF, MUTEX, 0, 8) > +REG32(TRANSITION_REGWEN , 0x0C) > + FIELD(TRANSITION_REGWEN , TRANSITION_REGWEN, 0, 1) > +REG32(TRANSITION_CMD , 0x10) > + FIELD(TRANSITION_CMD , START, 0, 1) > +REG32(TRANSITION_CTRL , 0x14) > + FIELD(TRANSITION_CTRL , EXT_CLOCK_EN, 0, 1) > +REG32(TRANSITION_TOKEN_0 , 0x18) > + FIELD(TRANSITION_TOKEN_0 , TRANSITION_TOKEN_0, 0, 32) > +REG32(TRANSITION_TOKEN_1 , 0x1C) > + FIELD(TRANSITION_TOKEN_1 , TRANSITION_TOKEN_1, 0, 32) > +REG32(TRANSITION_TOKEN_2 , 0x20) > + FIELD(TRANSITION_TOKEN_2 , TRANSITION_TOKEN_2, 0, 32) > +REG32(TRANSITION_TOKEN_3 , 0x24) > + FIELD(TRANSITION_TOKEN_3 , TRANSITION_TOKEN_3, 0, 32) > +REG32(TRANSITION_TARGET , 0x28) > + FIELD(TRANSITION_TARGET , STATE, 0, 30) > +REG32(OTP_VENDOR_TEST_CTRL , 0x2C) > + FIELD(OTP_VENDOR_TEST_CTRL , OTP_VENDOR_TEST_CTRL, 0, 32) > +REG32(OTP_VENDOR_TEST_STATUS , 0x30) > + FIELD(OTP_VENDOR_TEST_STATUS , OTP_VENDOR_TEST_STATUS, 0, 32) > +REG32(LC_STATE , 0x34) > + FIELD(LC_STATE , STATE, 0, 30) > +REG32(LC_TRANSITION_CNT , 0x38) > + FIELD(LC_TRANSITION_CNT , CNT, 0, 5) > +REG32(LC_ID_STATE , 0x3C) > + FIELD(LC_ID_STATE , STATE, 0, 32) > +REG32(HW_REV , 0x40) > + FIELD(HW_REV , CHIP_REV, 0, 16) > + FIELD(HW_REV , CHIP_GEN, 16, 16) > +REG32(DEVICE_ID_0 , 0x44) > + FIELD(DEVICE_ID_0 , DEVICE_ID_0, 0, 32) > +REG32(DEVICE_ID_1 , 0x48) > + FIELD(DEVICE_ID_1 , DEVICE_ID_2, 0, 32) > +REG32(DEVICE_ID_2 , 0x4C) > + FIELD(DEVICE_ID_2 , DEVICE_ID_2,
[PATCH v1 1/2] hw/misc: add ibex lifecycle controller
From: Wilfred Mallawa Device model for the OpenTitan lifecycle controller as per [1]. Addition of this model is the first of many steps to adding `boot_rom` support for OpenTitan. The OpenTitan `boot_rom` needs to access the lifecycle controller during the init/test sequence before it jumps to flash. With this model, we can get past the lifecycle controller stages in boot. Currently the supported functionality is limited. [1] https://docs.opentitan.org/hw/ip/lc_ctrl/doc/ Signed-off-by: Wilfred Mallawa --- hw/misc/ibex_lc_ctrl.c | 287 + hw/misc/meson.build| 3 + hw/misc/trace-events | 5 + include/hw/misc/ibex_lc_ctrl.h | 121 ++ 4 files changed, 416 insertions(+) create mode 100644 hw/misc/ibex_lc_ctrl.c create mode 100644 include/hw/misc/ibex_lc_ctrl.h diff --git a/hw/misc/ibex_lc_ctrl.c b/hw/misc/ibex_lc_ctrl.c new file mode 100644 index 00..f034a92a9c --- /dev/null +++ b/hw/misc/ibex_lc_ctrl.c @@ -0,0 +1,287 @@ +/* + * QEMU model of the Ibex Life Cycle Controller + * SPEC Reference: https://docs.opentitan.org/hw/ip/lc_ctrl/doc/ + * + * Copyright (C) 2022 Western Digital + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/misc/ibex_lc_ctrl.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "migration/vmstate.h" +#include "trace.h" + +REG32(ALERT_TEST, 0x00) +FIELD(ALERT_TEST, FETAL_PROG_ERR, 0, 1) +FIELD(ALERT_TEST, FETAL_STATE_ERR, 1, 1) +FIELD(ALERT_TEST, FETAL_BUS_INTEG_ERR, 2, 1) +REG32(CTRL_STATUS, 0x04) +FIELD(CTRL_STATUS, READY, 0, 1) +FIELD(CTRL_STATUS, TRANSITION_SUCCESSFUL, 0, 1) +FIELD(CTRL_STATUS, TRANSITION_COUNT_ERROR, 1, 1) +FIELD(CTRL_STATUS, TRANSITION_ERROR, 2, 1) +FIELD(CTRL_STATUS, TOKEN_ERROR, 3, 1) +FIELD(CTRL_STATUS, FLASH_RMA_ERROR, 4, 1) +FIELD(CTRL_STATUS, OTP_ERROR, 5, 1) +FIELD(CTRL_STATUS, STATE_ERROR, 6, 1) +FIELD(CTRL_STATUS, BUS_INTEG_ERROR, 7, 1) +FIELD(CTRL_STATUS, OTP_PARTITION_ERROR, 8, 1) +REG32(CLAIM_TRANSITION_IF, 0x08) + FIELD(CLAIM_TRANSITION_IF, MUTEX, 0, 8) +REG32(TRANSITION_REGWEN , 0x0C) + FIELD(TRANSITION_REGWEN , TRANSITION_REGWEN, 0, 1) +REG32(TRANSITION_CMD , 0x10) + FIELD(TRANSITION_CMD , START, 0, 1) +REG32(TRANSITION_CTRL , 0x14) + FIELD(TRANSITION_CTRL , EXT_CLOCK_EN, 0, 1) +REG32(TRANSITION_TOKEN_0 , 0x18) + FIELD(TRANSITION_TOKEN_0 , TRANSITION_TOKEN_0, 0, 32) +REG32(TRANSITION_TOKEN_1 , 0x1C) + FIELD(TRANSITION_TOKEN_1 , TRANSITION_TOKEN_1, 0, 32) +REG32(TRANSITION_TOKEN_2 , 0x20) + FIELD(TRANSITION_TOKEN_2 , TRANSITION_TOKEN_2, 0, 32) +REG32(TRANSITION_TOKEN_3 , 0x24) + FIELD(TRANSITION_TOKEN_3 , TRANSITION_TOKEN_3, 0, 32) +REG32(TRANSITION_TARGET , 0x28) + FIELD(TRANSITION_TARGET , STATE, 0, 30) +REG32(OTP_VENDOR_TEST_CTRL , 0x2C) + FIELD(OTP_VENDOR_TEST_CTRL , OTP_VENDOR_TEST_CTRL, 0, 32) +REG32(OTP_VENDOR_TEST_STATUS , 0x30) + FIELD(OTP_VENDOR_TEST_STATUS , OTP_VENDOR_TEST_STATUS, 0, 32) +REG32(LC_STATE , 0x34) + FIELD(LC_STATE , STATE, 0, 30) +REG32(LC_TRANSITION_CNT , 0x38) + FIELD(LC_TRANSITION_CNT , CNT, 0, 5) +REG32(LC_ID_STATE , 0x3C) + FIELD(LC_ID_STATE , STATE, 0, 32) +REG32(HW_REV , 0x40) + FIELD(HW_REV , CHIP_REV, 0, 16) + FIELD(HW_REV , CHIP_GEN, 16, 16) +REG32(DEVICE_ID_0 , 0x44) + FIELD(DEVICE_ID_0 , DEVICE_ID_0, 0, 32) +REG32(DEVICE_ID_1 , 0x48) + FIELD(DEVICE_ID_1 , DEVICE_ID_2, 0, 32) +REG32(DEVICE_ID_2 , 0x4C) + FIELD(DEVICE_ID_2 , DEVICE_ID_2, 0, 32) +REG32(DEVICE_ID_3 , 0x50) + FIELD(DEVICE_ID_3 , DEVICE_ID_3, 0, 32) +REG32(DEVICE_ID_4 , 0x54) + FIELD(DEVICE_ID_4 , DEVICE_ID_4, 0, 32) +REG32(DEVICE_ID_5 , 0x58) + FIELD(DEVICE_ID_5 , DEVICE_ID_5, 0, 32) +REG32(DEVICE_ID_6 , 0x5C) + FIELD(DEVICE_ID_6 , DEVICE_ID_6, 0,
