subject:"\[PATCH v1 4\/5\] RISC\-V\: Typed CSRs in gdbserver"

Re: [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver

2022-01-03 Thread Ralf Ramsauer





On 02/01/2022 17:06, Konrad Schwarz wrote:

GDB target descriptions support typed registers;
such that `info register X' displays not only the hex value of
register `X', but also the individual bitfields the register
comprises (if any), using textual labels if possible.

This patch includes type information for GDB for
a large subset of the RISC-V Control and Status Registers (CSRs).

Signed-off-by: Konrad Schwarz 
---
  target/riscv/csr.c|   2 +
  target/riscv/csr32-op-gdbserver.h | 109 ++
  target/riscv/csr64-op-gdbserver.h |  76 +++
  target/riscv/gdb_csr_types.c  | 333 ++
  target/riscv/gdb_csr_types.h  |   3 +
  target/riscv/gdbstub.c|  26 ++-
  target/riscv/meson.build  |   4 +-
  7 files changed, 547 insertions(+), 6 deletions(-)
  create mode 100644 target/riscv/csr32-op-gdbserver.h
  create mode 100644 target/riscv/csr64-op-gdbserver.h
  create mode 100644 target/riscv/gdb_csr_types.c
  create mode 100644 target/riscv/gdb_csr_types.h

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..557b4afe0e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3,6 +3,7 @@
   *
   * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
   * Copyright (c) 2017-2018 SiFive, Inc.
+ * Copyright (c) 2021 Siemens AG, konrad.schw...@siemens.com
   *
   * This program is free software; you can redistribute it and/or modify it
   * under the terms and conditions of the GNU General Public License,
@@ -2094,5 +2095,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
  [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
  [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
  [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
+
  #endif /* !CONFIG_USER_ONLY */
  };
diff --git a/target/riscv/csr32-op-gdbserver.h 
b/target/riscv/csr32-op-gdbserver.h
new file mode 100644
index 00..e8ec527f23
--- /dev/null
+++ b/target/riscv/csr32-op-gdbserver.h
@@ -0,0 +1,109 @@
+/* Copyright (c) 2021 Siemens AG, konrad.schw...@siemens.com */
+
+  [CSR_USTATUS] { .gdb_type = "sstatus-fields", .gdb_group = "user" },
+  [CSR_UIE] { .gdb_type = "sie-fields", .gdb_group = "user" },
+  [CSR_UTVEC] { .gdb_type = "code_ptr", .gdb_group = "user" },
+  [CSR_USCRATCH] { .gdb_type = "data_ptr", .gdb_group = "user" },
+  [CSR_UEPC] { .gdb_type = "code_ptr", .gdb_group = "user" },
+  [CSR_UCAUSE] { .gdb_type = "scause-fields", .gdb_group = "user" },
+  [CSR_UTVAL] { .gdb_type = "data_ptr", .gdb_group = "user" },
+  [CSR_UIP] { .gdb_type = "code_ptr", .gdb_group = "user" },
+  [CSR_CYCLE] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_TIME] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_INSTRET] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_HPMCOUNTER3] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER4] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER5] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER6] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER7] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER8] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER9] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER10] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER11] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER12] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER13] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER14] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER15] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER16] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER17] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER18] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER19] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER20] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER21] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER22] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER23] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER24] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER25] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER26] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER27] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER28] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER29] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER30] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER31] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_CYCLEH] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_TIMEH] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_INSTRETH] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_HPMCOUNTER3H] { .gdb_type = "int", .gdb_group = "use

[PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver

2022-01-02 Thread Konrad Schwarz

GDB target descriptions support typed registers;
such that `info register X' displays not only the hex value of
register `X', but also the individual bitfields the register
comprises (if any), using textual labels if possible.

This patch includes type information for GDB for
a large subset of the RISC-V Control and Status Registers (CSRs).

Signed-off-by: Konrad Schwarz 
---
 target/riscv/csr.c|   2 +
 target/riscv/csr32-op-gdbserver.h | 109 ++
 target/riscv/csr64-op-gdbserver.h |  76 +++
 target/riscv/gdb_csr_types.c  | 333 ++
 target/riscv/gdb_csr_types.h  |   3 +
 target/riscv/gdbstub.c|  26 ++-
 target/riscv/meson.build  |   4 +-
 7 files changed, 547 insertions(+), 6 deletions(-)
 create mode 100644 target/riscv/csr32-op-gdbserver.h
 create mode 100644 target/riscv/csr64-op-gdbserver.h
 create mode 100644 target/riscv/gdb_csr_types.c
 create mode 100644 target/riscv/gdb_csr_types.h

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..557b4afe0e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3,6 +3,7 @@
  *
  * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
  * Copyright (c) 2017-2018 SiFive, Inc.
+ * Copyright (c) 2021 Siemens AG, konrad.schw...@siemens.com
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -2094,5 +2095,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
+
 #endif /* !CONFIG_USER_ONLY */
 };
diff --git a/target/riscv/csr32-op-gdbserver.h 
b/target/riscv/csr32-op-gdbserver.h
new file mode 100644
index 00..e8ec527f23
--- /dev/null
+++ b/target/riscv/csr32-op-gdbserver.h
@@ -0,0 +1,109 @@
+/* Copyright (c) 2021 Siemens AG, konrad.schw...@siemens.com */
+
+  [CSR_USTATUS] { .gdb_type = "sstatus-fields", .gdb_group = "user" },
+  [CSR_UIE] { .gdb_type = "sie-fields", .gdb_group = "user" },
+  [CSR_UTVEC] { .gdb_type = "code_ptr", .gdb_group = "user" },
+  [CSR_USCRATCH] { .gdb_type = "data_ptr", .gdb_group = "user" },
+  [CSR_UEPC] { .gdb_type = "code_ptr", .gdb_group = "user" },
+  [CSR_UCAUSE] { .gdb_type = "scause-fields", .gdb_group = "user" },
+  [CSR_UTVAL] { .gdb_type = "data_ptr", .gdb_group = "user" },
+  [CSR_UIP] { .gdb_type = "code_ptr", .gdb_group = "user" },
+  [CSR_CYCLE] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_TIME] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_INSTRET] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_HPMCOUNTER3] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER4] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER5] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER6] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER7] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER8] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER9] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER10] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER11] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER12] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER13] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER14] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER15] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER16] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER17] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER18] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER19] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER20] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER21] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER22] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER23] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER24] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER25] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER26] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER27] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER28] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER29] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER30] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER31] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_CYCLEH] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_TIMEH] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_INSTRETH] { .gdb_type = "uint32", .gdb_group = "user" },
+  [CSR_HPMCOUNTER3H] { .gdb_type = "int", .gdb_group = "user" },
+  [CSR_HPMCOUNTER4H] { .gdb_type = "int", .gdb_group = "user" },

Re: [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver

[PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver

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