Re: [PATCH v1 6/7] hw/fsi: Aspeed APB2OPB interface
Hi Joel, On 8/28/23 23:55, Joel Stanley wrote: On Fri, 25 Aug 2023 at 20:31, Ninad Palsule wrote: This is a part of patchset where IBM's Flexible Service Interface is introduced. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge. Signed-off-by: Andrew Jeffery Signed-off-by: Cédric Le Goater Signed-off-by: Ninad Palsule --- hw/arm/Kconfig | 1 + hw/fsi/Kconfig | 4 + hw/fsi/aspeed-apb2opb.c | 346 hw/fsi/meson.build | 1 + hw/fsi/trace-events | 2 + hw/fsi/trace.h | 1 + include/hw/fsi/aspeed-apb2opb.h | 32 +++ meson.build | 1 + 8 files changed, 388 insertions(+) create mode 100644 hw/fsi/aspeed-apb2opb.c create mode 100644 hw/fsi/trace-events create mode 100644 hw/fsi/trace.h create mode 100644 include/hw/fsi/aspeed-apb2opb.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7e68348440..a6994cd9d7 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -589,6 +589,7 @@ config FSL_IMX7 select PCI_EXPRESS_DESIGNWARE select SDHCI select UNIMP +select APB2OPB_ASPEED config ARM_SMMUV3 bool diff --git a/hw/fsi/Kconfig b/hw/fsi/Kconfig index 560ce536db..fbb021658d 100644 --- a/hw/fsi/Kconfig +++ b/hw/fsi/Kconfig @@ -1,3 +1,7 @@ +config APB2OPB_ASPEED +bool +select OPB + config OPB bool select CFAM diff --git a/hw/fsi/aspeed-apb2opb.c b/hw/fsi/aspeed-apb2opb.c new file mode 100644 index 00..bbc63f2eb3 --- /dev/null +++ b/hw/fsi/aspeed-apb2opb.c @@ -0,0 +1,346 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (C) 2023 IBM Corp. + * + * ASPEED APB-OPB FSI interface + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "qapi/error.h" +#include "trace.h" + +#include "hw/fsi/aspeed-apb2opb.h" +#include "hw/qdev-core.h" + +#define TO_REG(x) (x >> 2) +#define GENMASK(t, b) (((1ULL << ((t) + 1)) - 1) & ~((1ULL << (b)) - 1)) We should put this in a common header. Moved it to bitops.h + +#define APB2OPB_VERSIONTO_REG(0x00) +#define APB2OPB_VERSION_VER GENMASK(7, 0) + +#define APB2OPB_TRIGGERTO_REG(0x04) +#define APB2OPB_TRIGGER_EN BIT(0) + +#define APB2OPB_CONTROLTO_REG(0x08) +#define APB2OPB_CONTROL_OFF GENMASK(31, 13) + +#define APB2OPB_OPB2FSITO_REG(0x0c) +#define APB2OPB_OPB2FSI_OFF GENMASK(31, 22) + +#define APB2OPB_OPB0_SEL TO_REG(0x10) +#define APB2OPB_OPB1_SEL TO_REG(0x28) +#define APB2OPB_OPB_SEL_EN BIT(0) + +#define APB2OPB_OPB0_MODE TO_REG(0x14) +#define APB2OPB_OPB1_MODE TO_REG(0x2c) +#define APB2OPB_OPB_MODE_RD BIT(0) + +#define APB2OPB_OPB0_XFER TO_REG(0x18) +#define APB2OPB_OPB1_XFER TO_REG(0x30) +#define APB2OPB_OPB_XFER_FULLBIT(1) +#define APB2OPB_OPB_XFER_HALFBIT(0) + +#define APB2OPB_OPB0_ADDR TO_REG(0x1c) +#define APB2OPB_OPB0_WRITE_DATATO_REG(0x20) + +#define APB2OPB_OPB1_DMA_ENTO_REG(0x24) +#define APB2OPB_OPB1_DMA_EN_3 BIT(3) +#define APB2OPB_OPB1_DMA_EN_2 BIT(2) +#define APB2OPB_OPB1_DMA_EN_1 BIT(1) +#define APB2OPB_OPB1_DMA_EN_0 BIT(0) + +#define APB2OPB_OPB1_ADDR TO_REG(0x34) +#define APB2OPB_OPB1_WRITE_DATA TO_REG(0x38) + +#define APB2OPB_OPB_CLKTO_REG(0x3c) +#define APB2OPB_OPB_CLK_SYNC BIT(0) + +#define APB2OPB_IRQ_CLEAR TO_REG(0x40) +#define APB2OPB_IRQ_CLEAR_EN BIT(0) + +#define APB2OPB_IRQ_MASK TO_REG(0x44) +#define APB2OPB_IRQ_MASK_OPB1_TX_ACK BIT(17) +#define APB2OPB_IRQ_MASK_OPB0_TX_ACK BIT(16) +#define APB2OPB_IRQ_MASK_CH3_TCONT BIT(15) +#define APB2OPB_IRQ_MASK_CH2_TCONT BIT(14) +#define APB2OPB_IRQ_MASK_CH1_TCONT BIT(13) +#define APB2OPB_IRQ_MASK_CH0_TCONT BIT(12) +#define APB2OPB_IRQ_MASK_CH3_FIFO_EMPTY BIT(11) +#define APB2OPB_IRQ_MASK_CH2_FIFO_EMPTY BIT(10) +#define APB2OPB_IRQ_MASK_CH1_FIFO_EMPTY BIT(9) +#define APB2OPB_IRQ_MASK_CH0_FIFO_EMPTY BIT(8) +#define APB2OPB_IRQ_MASK_CH3_FIFO_FULL BIT(7) +#define APB2OPB_IRQ_MASK_CH2_FIFO_FULL BIT(6) +#define APB2OPB_IRQ_MASK_CH1_FIFO_FULL BIT(5) +#define APB2OPB_IRQ_MASK_CH0_FIFO_FULL BIT(4) +#define APB2OPB_IRQ_MASK_CH3_DMA_EOT BIT(3) +#define APB2OPB_IRQ_MASK_CH2_DMA_EOT BIT(2) +#define APB2OPB_IRQ_MASK_CH1_DMA_EOT BIT(1) +#define APB2OPB_IRQ_MASK_CH0_DMA_EOT BIT(0) + +#define APB2OPB_IRQ_STS
Re: [PATCH v1 6/7] hw/fsi: Aspeed APB2OPB interface
On Fri, 25 Aug 2023 at 20:31, Ninad Palsule wrote: > > This is a part of patchset where IBM's Flexible Service Interface is > introduced. > > An APB-to-OPB bridge enabling access to the OPB from the ARM core in > the AST2600. Hardware limitations prevent the OPB from being directly > mapped into APB, so all accesses are indirect through the bridge. > > Signed-off-by: Andrew Jeffery > Signed-off-by: Cédric Le Goater > Signed-off-by: Ninad Palsule > --- > hw/arm/Kconfig | 1 + > hw/fsi/Kconfig | 4 + > hw/fsi/aspeed-apb2opb.c | 346 > hw/fsi/meson.build | 1 + > hw/fsi/trace-events | 2 + > hw/fsi/trace.h | 1 + > include/hw/fsi/aspeed-apb2opb.h | 32 +++ > meson.build | 1 + > 8 files changed, 388 insertions(+) > create mode 100644 hw/fsi/aspeed-apb2opb.c > create mode 100644 hw/fsi/trace-events > create mode 100644 hw/fsi/trace.h > create mode 100644 include/hw/fsi/aspeed-apb2opb.h > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 7e68348440..a6994cd9d7 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -589,6 +589,7 @@ config FSL_IMX7 > select PCI_EXPRESS_DESIGNWARE > select SDHCI > select UNIMP > +select APB2OPB_ASPEED > > config ARM_SMMUV3 > bool > diff --git a/hw/fsi/Kconfig b/hw/fsi/Kconfig > index 560ce536db..fbb021658d 100644 > --- a/hw/fsi/Kconfig > +++ b/hw/fsi/Kconfig > @@ -1,3 +1,7 @@ > +config APB2OPB_ASPEED > +bool > +select OPB > + > config OPB > bool > select CFAM > diff --git a/hw/fsi/aspeed-apb2opb.c b/hw/fsi/aspeed-apb2opb.c > new file mode 100644 > index 00..bbc63f2eb3 > --- /dev/null > +++ b/hw/fsi/aspeed-apb2opb.c > @@ -0,0 +1,346 @@ > +/* > + * SPDX-License-Identifier: GPL-2.0-or-later > + * Copyright (C) 2023 IBM Corp. > + * > + * ASPEED APB-OPB FSI interface > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "qom/object.h" > +#include "qapi/error.h" > +#include "trace.h" > + > +#include "hw/fsi/aspeed-apb2opb.h" > +#include "hw/qdev-core.h" > + > +#define TO_REG(x) (x >> 2) > +#define GENMASK(t, b) (((1ULL << ((t) + 1)) - 1) & ~((1ULL << (b)) - 1)) We should put this in a common header. > + > +#define APB2OPB_VERSIONTO_REG(0x00) > +#define APB2OPB_VERSION_VER GENMASK(7, 0) > + > +#define APB2OPB_TRIGGERTO_REG(0x04) > +#define APB2OPB_TRIGGER_EN BIT(0) > + > +#define APB2OPB_CONTROLTO_REG(0x08) > +#define APB2OPB_CONTROL_OFF GENMASK(31, 13) > + > +#define APB2OPB_OPB2FSITO_REG(0x0c) > +#define APB2OPB_OPB2FSI_OFF GENMASK(31, 22) > + > +#define APB2OPB_OPB0_SEL TO_REG(0x10) > +#define APB2OPB_OPB1_SEL TO_REG(0x28) > +#define APB2OPB_OPB_SEL_EN BIT(0) > + > +#define APB2OPB_OPB0_MODE TO_REG(0x14) > +#define APB2OPB_OPB1_MODE TO_REG(0x2c) > +#define APB2OPB_OPB_MODE_RD BIT(0) > + > +#define APB2OPB_OPB0_XFER TO_REG(0x18) > +#define APB2OPB_OPB1_XFER TO_REG(0x30) > +#define APB2OPB_OPB_XFER_FULLBIT(1) > +#define APB2OPB_OPB_XFER_HALFBIT(0) > + > +#define APB2OPB_OPB0_ADDR TO_REG(0x1c) > +#define APB2OPB_OPB0_WRITE_DATATO_REG(0x20) > + > +#define APB2OPB_OPB1_DMA_ENTO_REG(0x24) > +#define APB2OPB_OPB1_DMA_EN_3 BIT(3) > +#define APB2OPB_OPB1_DMA_EN_2 BIT(2) > +#define APB2OPB_OPB1_DMA_EN_1 BIT(1) > +#define APB2OPB_OPB1_DMA_EN_0 BIT(0) > + > +#define APB2OPB_OPB1_ADDR TO_REG(0x34) > +#define APB2OPB_OPB1_WRITE_DATA TO_REG(0x38) > + > +#define APB2OPB_OPB_CLKTO_REG(0x3c) > +#define APB2OPB_OPB_CLK_SYNC BIT(0) > + > +#define APB2OPB_IRQ_CLEAR TO_REG(0x40) > +#define APB2OPB_IRQ_CLEAR_EN BIT(0) > + > +#define APB2OPB_IRQ_MASK TO_REG(0x44) > +#define APB2OPB_IRQ_MASK_OPB1_TX_ACK BIT(17) > +#define APB2OPB_IRQ_MASK_OPB0_TX_ACK BIT(16) > +#define APB2OPB_IRQ_MASK_CH3_TCONT BIT(15) > +#define APB2OPB_IRQ_MASK_CH2_TCONT BIT(14) > +#define APB2OPB_IRQ_MASK_CH1_TCONT BIT(13) > +#define APB2OPB_IRQ_MASK_CH0_TCONT BIT(12) > +#define APB2OPB_IRQ_MASK_CH3_FIFO_EMPTY BIT(11) > +#define APB2OPB_IRQ_MASK_CH2_FIFO_EMPTY BIT(10) > +#define APB2OPB_IRQ_MASK_CH1_FIFO_EMPTY BIT(9) > +#define APB2OPB_IRQ_MASK_CH0_FIFO_EMPTY BIT(8) > +#define APB2OPB_IRQ_MASK_CH3_FIFO_FULL BIT(7) > +#define APB2OPB_IRQ_MASK_CH2_FIFO_FULL BIT(6) > +#define APB2OPB_IRQ_MASK_CH1_FIFO_FULL BIT(5) > +#define APB2OPB_IRQ_MASK_CH0_FIFO_FULL BIT(4) > +#define APB2OPB_IRQ_MASK_CH3_DMA_EOT BIT(3) > +#define
[PATCH v1 6/7] hw/fsi: Aspeed APB2OPB interface
This is a part of patchset where IBM's Flexible Service Interface is introduced. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge. Signed-off-by: Andrew Jeffery Signed-off-by: Cédric Le Goater Signed-off-by: Ninad Palsule --- hw/arm/Kconfig | 1 + hw/fsi/Kconfig | 4 + hw/fsi/aspeed-apb2opb.c | 346 hw/fsi/meson.build | 1 + hw/fsi/trace-events | 2 + hw/fsi/trace.h | 1 + include/hw/fsi/aspeed-apb2opb.h | 32 +++ meson.build | 1 + 8 files changed, 388 insertions(+) create mode 100644 hw/fsi/aspeed-apb2opb.c create mode 100644 hw/fsi/trace-events create mode 100644 hw/fsi/trace.h create mode 100644 include/hw/fsi/aspeed-apb2opb.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7e68348440..a6994cd9d7 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -589,6 +589,7 @@ config FSL_IMX7 select PCI_EXPRESS_DESIGNWARE select SDHCI select UNIMP +select APB2OPB_ASPEED config ARM_SMMUV3 bool diff --git a/hw/fsi/Kconfig b/hw/fsi/Kconfig index 560ce536db..fbb021658d 100644 --- a/hw/fsi/Kconfig +++ b/hw/fsi/Kconfig @@ -1,3 +1,7 @@ +config APB2OPB_ASPEED +bool +select OPB + config OPB bool select CFAM diff --git a/hw/fsi/aspeed-apb2opb.c b/hw/fsi/aspeed-apb2opb.c new file mode 100644 index 00..bbc63f2eb3 --- /dev/null +++ b/hw/fsi/aspeed-apb2opb.c @@ -0,0 +1,346 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (C) 2023 IBM Corp. + * + * ASPEED APB-OPB FSI interface + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "qapi/error.h" +#include "trace.h" + +#include "hw/fsi/aspeed-apb2opb.h" +#include "hw/qdev-core.h" + +#define TO_REG(x) (x >> 2) +#define GENMASK(t, b) (((1ULL << ((t) + 1)) - 1) & ~((1ULL << (b)) - 1)) + +#define APB2OPB_VERSIONTO_REG(0x00) +#define APB2OPB_VERSION_VER GENMASK(7, 0) + +#define APB2OPB_TRIGGERTO_REG(0x04) +#define APB2OPB_TRIGGER_EN BIT(0) + +#define APB2OPB_CONTROLTO_REG(0x08) +#define APB2OPB_CONTROL_OFF GENMASK(31, 13) + +#define APB2OPB_OPB2FSITO_REG(0x0c) +#define APB2OPB_OPB2FSI_OFF GENMASK(31, 22) + +#define APB2OPB_OPB0_SEL TO_REG(0x10) +#define APB2OPB_OPB1_SEL TO_REG(0x28) +#define APB2OPB_OPB_SEL_EN BIT(0) + +#define APB2OPB_OPB0_MODE TO_REG(0x14) +#define APB2OPB_OPB1_MODE TO_REG(0x2c) +#define APB2OPB_OPB_MODE_RD BIT(0) + +#define APB2OPB_OPB0_XFER TO_REG(0x18) +#define APB2OPB_OPB1_XFER TO_REG(0x30) +#define APB2OPB_OPB_XFER_FULLBIT(1) +#define APB2OPB_OPB_XFER_HALFBIT(0) + +#define APB2OPB_OPB0_ADDR TO_REG(0x1c) +#define APB2OPB_OPB0_WRITE_DATATO_REG(0x20) + +#define APB2OPB_OPB1_DMA_ENTO_REG(0x24) +#define APB2OPB_OPB1_DMA_EN_3 BIT(3) +#define APB2OPB_OPB1_DMA_EN_2 BIT(2) +#define APB2OPB_OPB1_DMA_EN_1 BIT(1) +#define APB2OPB_OPB1_DMA_EN_0 BIT(0) + +#define APB2OPB_OPB1_ADDR TO_REG(0x34) +#define APB2OPB_OPB1_WRITE_DATA TO_REG(0x38) + +#define APB2OPB_OPB_CLKTO_REG(0x3c) +#define APB2OPB_OPB_CLK_SYNC BIT(0) + +#define APB2OPB_IRQ_CLEAR TO_REG(0x40) +#define APB2OPB_IRQ_CLEAR_EN BIT(0) + +#define APB2OPB_IRQ_MASK TO_REG(0x44) +#define APB2OPB_IRQ_MASK_OPB1_TX_ACK BIT(17) +#define APB2OPB_IRQ_MASK_OPB0_TX_ACK BIT(16) +#define APB2OPB_IRQ_MASK_CH3_TCONT BIT(15) +#define APB2OPB_IRQ_MASK_CH2_TCONT BIT(14) +#define APB2OPB_IRQ_MASK_CH1_TCONT BIT(13) +#define APB2OPB_IRQ_MASK_CH0_TCONT BIT(12) +#define APB2OPB_IRQ_MASK_CH3_FIFO_EMPTY BIT(11) +#define APB2OPB_IRQ_MASK_CH2_FIFO_EMPTY BIT(10) +#define APB2OPB_IRQ_MASK_CH1_FIFO_EMPTY BIT(9) +#define APB2OPB_IRQ_MASK_CH0_FIFO_EMPTY BIT(8) +#define APB2OPB_IRQ_MASK_CH3_FIFO_FULL BIT(7) +#define APB2OPB_IRQ_MASK_CH2_FIFO_FULL BIT(6) +#define APB2OPB_IRQ_MASK_CH1_FIFO_FULL BIT(5) +#define APB2OPB_IRQ_MASK_CH0_FIFO_FULL BIT(4) +#define APB2OPB_IRQ_MASK_CH3_DMA_EOT BIT(3) +#define APB2OPB_IRQ_MASK_CH2_DMA_EOT BIT(2) +#define APB2OPB_IRQ_MASK_CH1_DMA_EOT BIT(1) +#define APB2OPB_IRQ_MASK_CH0_DMA_EOT BIT(0) + +#define APB2OPB_IRQ_STSTO_REG(0x48) +#define APB2OPB_IRQ_STS_MASTER_ERROR BIT(28) +#define APB2OPB_IRQ_STS_PORT_ERROR BIT(27) +#define APB2OPB_IRQ_STS_HOTPLUG BIT(26)
