Re: [PATCH v10 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
On Mon, Nov 29, 2021 at 1:54 PM wrote:
>
> From: Frank Chang
>
> SEW has the limitation which cannot exceed ELEN.
>
> Widening instructions have a destination group with EEW = 2*SEW
> and narrowing instructions have a source operand with EEW = 2*SEW.
> Both of the instructions have the limitation of: 2*SEW <= ELEN.
>
> Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 17 +++--
> target/riscv/translate.c| 2 ++
> 2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 47eb3119cbe..5e3f7fdb77c 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -386,9 +386,10 @@ static bool vext_check_mss(DisasContext *s, int vd, int
> vs1, int vs2)
> * can not be greater than 8 vector registers (Section 5.2):
> * => LMUL < 8.
> * => SEW < 64.
> - * 2. Destination vector register number is multiples of 2 * LMUL.
> + * 2. Double-width SEW cannot greater than ELEN.
> + * 3. Destination vector register number is multiples of 2 * LMUL.
> * (Section 3.4.2)
> - * 3. Destination vector register group for a masked vector
> + * 4. Destination vector register group for a masked vector
> * instruction cannot overlap the source mask register (v0).
> * (Section 5.3)
> */
> @@ -396,6 +397,7 @@ static bool vext_wide_check_common(DisasContext *s, int
> vd, int vm)
> {
> return (s->lmul <= 2) &&
> (s->sew < MO_64) &&
> + ((s->sew + 1) <= (s->elen >> 4)) &&
> require_align(vd, s->lmul + 1) &&
> require_vm(vm, vd);
> }
> @@ -409,11 +411,12 @@ static bool vext_wide_check_common(DisasContext *s, int
> vd, int vm)
> * can not be greater than 8 vector registers (Section 5.2):
> * => LMUL < 8.
> * => SEW < 64.
> - * 2. Source vector register number is multiples of 2 * LMUL.
> + * 2. Double-width SEW cannot greater than ELEN.
> + * 3. Source vector register number is multiples of 2 * LMUL.
> * (Section 3.4.2)
> - * 3. Destination vector register number is multiples of LMUL.
> + * 4. Destination vector register number is multiples of LMUL.
> * (Section 3.4.2)
> - * 4. Destination vector register group for a masked vector
> + * 5. Destination vector register group for a masked vector
> * instruction cannot overlap the source mask register (v0).
> * (Section 5.3)
> */
> @@ -422,6 +425,7 @@ static bool vext_narrow_check_common(DisasContext *s, int
> vd, int vs2,
> {
> return (s->lmul <= 2) &&
> (s->sew < MO_64) &&
> + ((s->sew + 1) <= (s->elen >> 4)) &&
> require_align(vs2, s->lmul + 1) &&
> require_align(vd, s->lmul) &&
> require_vm(vm, vd);
> @@ -2806,7 +2810,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
> /* Vector Widening Integer Reduction Instructions */
> static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
> {
> -return reduction_check(s, a) && (s->sew < MO_64);
> +return reduction_check(s, a) && (s->sew < MO_64) &&
> + ((s->sew + 1) <= (s->elen >> 4));
> }
>
> GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 68edaaf6ac7..5df6c0d800b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -96,6 +96,7 @@ typedef struct DisasContext {
> int8_t lmul;
> uint8_t sew;
> uint16_t vlen;
> +uint16_t elen;
> target_ulong vstart;
> bool vl_eq_vlmax;
> uint8_t ntemp;
> @@ -705,6 +706,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
> *dcbase, CPUState *cs)
> ctx->ext_zfh = cpu->cfg.ext_zfh;
> ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
> ctx->vlen = cpu->cfg.vlen;
> +ctx->elen = cpu->cfg.elen;
> ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
> ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
> ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
> --
> 2.25.1
>
>
[PATCH v10 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
From: Frank Chang
SEW has the limitation which cannot exceed ELEN.
Widening instructions have a destination group with EEW = 2*SEW
and narrowing instructions have a source operand with EEW = 2*SEW.
Both of the instructions have the limitation of: 2*SEW <= ELEN.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 17 +++--
target/riscv/translate.c| 2 ++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 47eb3119cbe..5e3f7fdb77c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -386,9 +386,10 @@ static bool vext_check_mss(DisasContext *s, int vd, int
vs1, int vs2)
* can not be greater than 8 vector registers (Section 5.2):
* => LMUL < 8.
* => SEW < 64.
- * 2. Destination vector register number is multiples of 2 * LMUL.
+ * 2. Double-width SEW cannot greater than ELEN.
+ * 3. Destination vector register number is multiples of 2 * LMUL.
* (Section 3.4.2)
- * 3. Destination vector register group for a masked vector
+ * 4. Destination vector register group for a masked vector
* instruction cannot overlap the source mask register (v0).
* (Section 5.3)
*/
@@ -396,6 +397,7 @@ static bool vext_wide_check_common(DisasContext *s, int vd,
int vm)
{
return (s->lmul <= 2) &&
(s->sew < MO_64) &&
+ ((s->sew + 1) <= (s->elen >> 4)) &&
require_align(vd, s->lmul + 1) &&
require_vm(vm, vd);
}
@@ -409,11 +411,12 @@ static bool vext_wide_check_common(DisasContext *s, int
vd, int vm)
* can not be greater than 8 vector registers (Section 5.2):
* => LMUL < 8.
* => SEW < 64.
- * 2. Source vector register number is multiples of 2 * LMUL.
+ * 2. Double-width SEW cannot greater than ELEN.
+ * 3. Source vector register number is multiples of 2 * LMUL.
* (Section 3.4.2)
- * 3. Destination vector register number is multiples of LMUL.
+ * 4. Destination vector register number is multiples of LMUL.
* (Section 3.4.2)
- * 4. Destination vector register group for a masked vector
+ * 5. Destination vector register group for a masked vector
* instruction cannot overlap the source mask register (v0).
* (Section 5.3)
*/
@@ -422,6 +425,7 @@ static bool vext_narrow_check_common(DisasContext *s, int
vd, int vs2,
{
return (s->lmul <= 2) &&
(s->sew < MO_64) &&
+ ((s->sew + 1) <= (s->elen >> 4)) &&
require_align(vs2, s->lmul + 1) &&
require_align(vd, s->lmul) &&
require_vm(vm, vd);
@@ -2806,7 +2810,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
/* Vector Widening Integer Reduction Instructions */
static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
{
-return reduction_check(s, a) && (s->sew < MO_64);
+return reduction_check(s, a) && (s->sew < MO_64) &&
+ ((s->sew + 1) <= (s->elen >> 4));
}
GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 68edaaf6ac7..5df6c0d800b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -96,6 +96,7 @@ typedef struct DisasContext {
int8_t lmul;
uint8_t sew;
uint16_t vlen;
+uint16_t elen;
target_ulong vstart;
bool vl_eq_vlmax;
uint8_t ntemp;
@@ -705,6 +706,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->ext_zfh = cpu->cfg.ext_zfh;
ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
ctx->vlen = cpu->cfg.vlen;
+ctx->elen = cpu->cfg.elen;
ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
--
2.25.1
