Re: [PATCH v2 0/8] target/riscv: Improve RISC-V Debug support
On Fri, Sep 9, 2022 at 11:48 PM Bin Meng wrote:
>
> This patchset refactors RISC-V Debug support to allow more types of
> triggers to be extended.
>
> The initial support of type 6 trigger, which is similar to type 2
> trigger with additional functionality, is also introduced in this
> patchset.
>
> This is a v2 respin of previous patch originally done by Frank Chang
> at SiFive. I've incorperated my review comments in v2 and rebased
> against QEMU mainline.
>
> Changes in v2:
> - fixed MXL_RV128 case
> - moved macros to patch#2
> - added log guest errors for TRIGGER_TYPE_{NO_EXIST,UNAVAIL}
> - moved RV{32,64}_DATA_MASK definition to this patch
> - add handling of the DBG_ACTION_NONE case in do_trigger_action()
> - drop patch: "target/riscv: debug: Return 0 if previous value written to
> tselect >= number of triggers"
>
> Frank Chang (8):
> target/riscv: debug: Determine the trigger type from tdata1.type
> target/riscv: debug: Introduce build_tdata1() to build tdata1 register
> content
> target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
> target/riscv: debug: Restrict the range of tselect value can be
> written
> target/riscv: debug: Introduce tinfo CSR
> target/riscv: debug: Create common trigger actions function
> target/riscv: debug: Check VU/VS modes for type 2 trigger
> target/riscv: debug: Add initial support of type 6 trigger
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.h | 6 +-
> target/riscv/cpu_bits.h | 1 +
> target/riscv/debug.h| 55 +++--
> target/riscv/csr.c | 10 +-
> target/riscv/debug.c| 484
> target/riscv/machine.c | 20 +-
> 6 files changed, 445 insertions(+), 131 deletions(-)
>
> --
> 2.34.1
>
>
[PATCH v2 0/8] target/riscv: Improve RISC-V Debug support
This patchset refactors RISC-V Debug support to allow more types of
triggers to be extended.
The initial support of type 6 trigger, which is similar to type 2
trigger with additional functionality, is also introduced in this
patchset.
This is a v2 respin of previous patch originally done by Frank Chang
at SiFive. I've incorperated my review comments in v2 and rebased
against QEMU mainline.
Changes in v2:
- fixed MXL_RV128 case
- moved macros to patch#2
- added log guest errors for TRIGGER_TYPE_{NO_EXIST,UNAVAIL}
- moved RV{32,64}_DATA_MASK definition to this patch
- add handling of the DBG_ACTION_NONE case in do_trigger_action()
- drop patch: "target/riscv: debug: Return 0 if previous value written to
tselect >= number of triggers"
Frank Chang (8):
target/riscv: debug: Determine the trigger type from tdata1.type
target/riscv: debug: Introduce build_tdata1() to build tdata1 register
content
target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
target/riscv: debug: Restrict the range of tselect value can be
written
target/riscv: debug: Introduce tinfo CSR
target/riscv: debug: Create common trigger actions function
target/riscv: debug: Check VU/VS modes for type 2 trigger
target/riscv: debug: Add initial support of type 6 trigger
target/riscv/cpu.h | 6 +-
target/riscv/cpu_bits.h | 1 +
target/riscv/debug.h| 55 +++--
target/riscv/csr.c | 10 +-
target/riscv/debug.c| 484
target/riscv/machine.c | 20 +-
6 files changed, 445 insertions(+), 131 deletions(-)
--
2.34.1
