Re: [PATCH v2 06/23] target/i386: Create gen_update_eip_next

2022-09-21 Thread Paolo Bonzini 
On Tue, Sep 6, 2022 at 12:09 PM Richard Henderson
 wrote:
>
> Sync EIP before exiting a translation block.
> Replace all gen_jmp_im that use s->pc.
>
> Signed-off-by: Richard Henderson 
> ---
>  target/i386/tcg/translate.c | 45 -
>  1 file changed, 25 insertions(+), 20 deletions(-)

Reviewed-by: Paolo Bonzini 

>
> diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
> index 83cb925571..6084c85609 100644
> --- a/target/i386/tcg/translate.c
> +++ b/target/i386/tcg/translate.c
> @@ -521,6 +521,11 @@ static void gen_update_eip_cur(DisasContext *s)
>  gen_jmp_im(s, s->base.pc_next - s->cs_base);
>  }
>
> +static void gen_update_eip_next(DisasContext *s)
> +{
> +gen_jmp_im(s, s->pc - s->cs_base);
> +}
> +
>  /* Compute SEG:REG into A0.  SEG is selected from the override segment
> (OVR_SEG) and the default segment (DEF_SEG).  OVR_SEG may be -1 to
> indicate no override.  */
> @@ -5675,7 +5680,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
>  gen_pop_update(s, ot);
>  /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp.  */
>  if (s->base.is_jmp) {
> -gen_jmp_im(s, s->pc - s->cs_base);
> +gen_update_eip_next(s);
>  if (reg == R_SS) {
>  s->flags &= ~HF_TF_MASK;
>  gen_eob_inhibit_irq(s, true);
> @@ -5690,7 +5695,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
>  gen_movl_seg_T0(s, (b >> 3) & 7);
>  gen_pop_update(s, ot);
>  if (s->base.is_jmp) {
> -gen_jmp_im(s, s->pc - s->cs_base);
> +gen_update_eip_next(s);
>  gen_eob(s);
>  }
>  break;
> @@ -5741,7 +5746,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
>  gen_movl_seg_T0(s, reg);
>  /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp.  */
>  if (s->base.is_jmp) {
> -gen_jmp_im(s, s->pc - s->cs_base);
> +gen_update_eip_next(s);
>  if (reg == R_SS) {
>  s->flags &= ~HF_TF_MASK;
>  gen_eob_inhibit_irq(s, true);
> @@ -5948,7 +5953,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
>  /* then put the data */
>  gen_op_mov_reg_v(s, ot, reg, s->T1);
>  if (s->base.is_jmp) {
> -gen_jmp_im(s, s->pc - s->cs_base);
> +gen_update_eip_next(s);
>  gen_eob(s);
>  }
>  break;
> @@ -7004,7 +7009,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
>  gen_pop_update(s, ot);
>  set_cc_op(s, CC_OP_EFLAGS);
>  /* abort translation because TF/AC flag may change */
> -gen_jmp_im(s, s->pc - s->cs_base);
> +gen_update_eip_next(s);
>  gen_eob(s);
>  }
>  break;
> @@ -7340,7 +7345,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
>  if (check_iopl(s)) {
>  gen_helper_sti(cpu_env);
>  /* interruptions are enabled only the first insn after sti */
> -gen_jmp_im(s, s->pc - s->cs_base);
> +gen_update_eip_next(s);
>  gen_eob_inhibit_irq(s, true);
>  }
>  break;
> @@ -7416,7 +7421,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
>  }
>
>  gen_set_label(l3);
> -gen_jmp_im(s, next_eip);
> +gen_update_eip_next(s);
>  tcg_gen_br(l2);
>
>  gen_set_label(l1);
> @@ -7434,7 +7439,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
>  gen_helper_rdmsr(cpu_env);
>  } else {
>  gen_helper_wrmsr(cpu_env);
> -gen_jmp_im(s, s->pc - s->cs_base);
> +gen_update_eip_next(s);
>  gen_eob(s);
>  }
>  }
> @@ -7634,7 +7639,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
>  goto illegal_op;
>  }
>  gen_helper_clac(cpu_env);
> -gen_jmp_im(s, s->pc - s->cs_base);
> +gen_update_eip_next(s);
>  gen_eob(s);
>  break;
>
> @@ -7644,7 +7649,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
>  goto illegal_op;
>  }
>  gen_helper_stac(cpu_env);
> -gen_jmp_im(s, s->pc - s->cs_base);
> +gen_update_eip_next(s);
>  gen_eob(s);
>  break;
>
> @@ -7689,7 +7694,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
>  tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
>  gen_helper_xsetbv(cpu_env, s->tmp2_i32, s->tmp1_i64);
>  /* End TB because translation flags may change.  */
> -gen_jmp_im(s, s->pc - s->cs_base);
> +gen_update_eip_next(s);
>  gen_eob(s);
>  break;
>
> @@ -7751,7 +7756,7 @@ static bool

[PATCH v2 06/23] target/i386: Create gen_update_eip_next

2022-09-06 Thread Richard Henderson 
Sync EIP before exiting a translation block.
Replace all gen_jmp_im that use s->pc.

Signed-off-by: Richard Henderson 
---
 target/i386/tcg/translate.c | 45 -
 1 file changed, 25 insertions(+), 20 deletions(-)

diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 83cb925571..6084c85609 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -521,6 +521,11 @@ static void gen_update_eip_cur(DisasContext *s)
 gen_jmp_im(s, s->base.pc_next - s->cs_base);
 }
 
+static void gen_update_eip_next(DisasContext *s)
+{
+gen_jmp_im(s, s->pc - s->cs_base);
+}
+
 /* Compute SEG:REG into A0.  SEG is selected from the override segment
(OVR_SEG) and the default segment (DEF_SEG).  OVR_SEG may be -1 to
indicate no override.  */
@@ -5675,7 +5680,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 gen_pop_update(s, ot);
 /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp.  */
 if (s->base.is_jmp) {
-gen_jmp_im(s, s->pc - s->cs_base);
+gen_update_eip_next(s);
 if (reg == R_SS) {
 s->flags &= ~HF_TF_MASK;
 gen_eob_inhibit_irq(s, true);
@@ -5690,7 +5695,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 gen_movl_seg_T0(s, (b >> 3) & 7);
 gen_pop_update(s, ot);
 if (s->base.is_jmp) {
-gen_jmp_im(s, s->pc - s->cs_base);
+gen_update_eip_next(s);
 gen_eob(s);
 }
 break;
@@ -5741,7 +5746,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 gen_movl_seg_T0(s, reg);
 /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp.  */
 if (s->base.is_jmp) {
-gen_jmp_im(s, s->pc - s->cs_base);
+gen_update_eip_next(s);
 if (reg == R_SS) {
 s->flags &= ~HF_TF_MASK;
 gen_eob_inhibit_irq(s, true);
@@ -5948,7 +5953,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 /* then put the data */
 gen_op_mov_reg_v(s, ot, reg, s->T1);
 if (s->base.is_jmp) {
-gen_jmp_im(s, s->pc - s->cs_base);
+gen_update_eip_next(s);
 gen_eob(s);
 }
 break;
@@ -7004,7 +7009,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 gen_pop_update(s, ot);
 set_cc_op(s, CC_OP_EFLAGS);
 /* abort translation because TF/AC flag may change */
-gen_jmp_im(s, s->pc - s->cs_base);
+gen_update_eip_next(s);
 gen_eob(s);
 }
 break;
@@ -7340,7 +7345,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 if (check_iopl(s)) {
 gen_helper_sti(cpu_env);
 /* interruptions are enabled only the first insn after sti */
-gen_jmp_im(s, s->pc - s->cs_base);
+gen_update_eip_next(s);
 gen_eob_inhibit_irq(s, true);
 }
 break;
@@ -7416,7 +7421,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 }
 
 gen_set_label(l3);
-gen_jmp_im(s, next_eip);
+gen_update_eip_next(s);
 tcg_gen_br(l2);
 
 gen_set_label(l1);
@@ -7434,7 +7439,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 gen_helper_rdmsr(cpu_env);
 } else {
 gen_helper_wrmsr(cpu_env);
-gen_jmp_im(s, s->pc - s->cs_base);
+gen_update_eip_next(s);
 gen_eob(s);
 }
 }
@@ -7634,7 +7639,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 goto illegal_op;
 }
 gen_helper_clac(cpu_env);
-gen_jmp_im(s, s->pc - s->cs_base);
+gen_update_eip_next(s);
 gen_eob(s);
 break;
 
@@ -7644,7 +7649,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 goto illegal_op;
 }
 gen_helper_stac(cpu_env);
-gen_jmp_im(s, s->pc - s->cs_base);
+gen_update_eip_next(s);
 gen_eob(s);
 break;
 
@@ -7689,7 +7694,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
 gen_helper_xsetbv(cpu_env, s->tmp2_i32, s->tmp1_i64);
 /* End TB because translation flags may change.  */
-gen_jmp_im(s, s->pc - s->cs_base);
+gen_update_eip_next(s);
 gen_eob(s);
 break;
 
@@ -7751,7 +7756,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
 }
 gen_update_cc_op(s);
 gen_helper_stgi(cpu_env);
-gen_jmp_im(s, s->pc - s->cs_base);
+gen_update_eip_next(s);
 gen_eob(s);
 break;
 
@@ -7790,7 +7795,7 @@ static bool disas_insn(DisasContext