[PATCH v2 1/6] i386: Introduce FeatureWordInfo for AMX CPUID leaf 0x1D and 0x1E
CPUID leaf 0x1D and 0x1E enumerate tile and TMUL information for AMX.
Introduce FeatureWord FEAT_1D_1_EAX, FEAT_1D_1_EBX, FEAT_1D_1_ECX and
FEAT_1E_0_EBX. Thus these features of AMX can be expanded when
"-cpu host/max" and can be configured in named CPU model.
Signed-off-by: Wang, Lei
---
target/i386/cpu.c | 55 +++
target/i386/cpu.h | 12 +++
2 files changed, 67 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8a11470507..e98780773c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1002,6 +1002,45 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = ~0U,
},
+[FEAT_1D_1_EAX] = {
+.type = CPUID_FEATURE_WORD,
+.cpuid = {
+.eax = 0x1D,
+.needs_ecx = true, .ecx = 1,
+.reg = R_EAX,
+},
+.migratable_flags = CPUID_AMX_PALETTE_1_TOTAL_TILE_BYTES_MASK |
+CPUID_AMX_PALETTE_1_BYTES_PER_TILE_MASK,
+},
+[FEAT_1D_1_EBX] = {
+.type = CPUID_FEATURE_WORD,
+.cpuid = {
+.eax = 0x1D,
+.needs_ecx = true, .ecx = 1,
+.reg = R_EBX,
+},
+.migratable_flags = CPUID_AMX_PALETTE_1_BYTES_PER_ROW_MASK |
+CPUID_AMX_PALETTE_1_MAX_NAMES_MASK,
+},
+[FEAT_1D_1_ECX] = {
+.type = CPUID_FEATURE_WORD,
+.cpuid = {
+.eax = 0x1D,
+.needs_ecx = true, .ecx = 1,
+.reg = R_ECX,
+},
+.migratable_flags = CPUID_AMX_PALETTE_1_MAX_ROWS_MASK,
+},
+[FEAT_1E_0_EBX] = {
+.type = CPUID_FEATURE_WORD,
+.cpuid = {
+.eax = 0x1E,
+.needs_ecx = true, .ecx = 0,
+.reg = R_EBX,
+},
+.migratable_flags = CPUID_AMX_TMUL_MAX_K_MASK |
+CPUID_AMX_TMUL_MAX_N_MASK,
+},
/*Below are MSR exposed features*/
[FEAT_ARCH_CAPABILITIES] = {
.type = MSR_FEATURE_WORD,
@@ -1371,6 +1410,22 @@ static FeatureDep feature_dependencies[] = {
.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
.to = { FEAT_14_0_ECX, ~0ull },
},
+{
+.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE },
+.to = { FEAT_1D_1_EAX, ~0ull },
+},
+{
+.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE },
+.to = { FEAT_1D_1_EBX, ~0ull },
+},
+{
+.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE },
+.to = { FEAT_1D_1_ECX, ~0ull },
+},
+{
+.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE },
+.to = { FEAT_1E_0_EBX, ~0ull },
+},
{
.from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
.to = { FEAT_VMX_SECONDARY_CTLS,VMX_SECONDARY_EXEC_RDTSCP },
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7edf5dfac3..1c90fb6c9d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -583,6 +583,14 @@ typedef enum X86Seg {
XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
XSTATE_XTILE_CFG_MASK |
XSTATE_XTILE_DATA_MASK)
+#define CPUID_AMX_PALETTE_1_TOTAL_TILE_BYTES_MASK 0xU
+#define CPUID_AMX_PALETTE_1_BYTES_PER_TILE_MASK (0xU << 16)
+#define CPUID_AMX_PALETTE_1_BYTES_PER_ROW_MASK0xU
+#define CPUID_AMX_PALETTE_1_MAX_NAMES_MASK(0xU << 16)
+#define CPUID_AMX_PALETTE_1_MAX_ROWS_MASK 0xU
+#define CPUID_AMX_TMUL_MAX_K_MASK 0xffU
+#define CPUID_AMX_TMUL_MAX_N_MASK (0xU << 8)
+
/* CPUID feature words */
typedef enum FeatureWord {
FEAT_1_EDX, /* CPUID[1].EDX */
@@ -603,6 +611,10 @@ typedef enum FeatureWord {
FEAT_6_EAX, /* CPUID[6].EAX */
FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
+FEAT_1D_1_EAX, /* CPUID[EAX=0x1d,ECX=1].EAX */
+FEAT_1D_1_EBX, /* CPUID[EAX=0x1d,ECX=1].EBX */
+FEAT_1D_1_ECX, /* CPUID[EAX=0x1d,ECX=1].ECX */
+FEAT_1E_0_EBX, /* CPUID[EAX=0x1e,ECX=0].EBX */
FEAT_ARCH_CAPABILITIES,
FEAT_CORE_CAPABILITY,
FEAT_PERF_CAPABILITIES,
--
2.34.1
[PATCH v2 1/6] i386: Introduce FeatureWordInfo for AMX CPUID leaf 0x1D and 0x1E
CPUID leaf 0x1D and 0x1E enumerate tile and TMUL information for AMX.
Introduce FeatureWord FEAT_1D_1_EAX, FEAT_1D_1_EBX, FEAT_1D_1_ECX and
FEAT_1E_0_EBX. Thus these features of AMX can be expanded when
"-cpu host/max" and can be configured in named CPU model.
Signed-off-by: Wang, Lei
---
target/i386/cpu.c | 55 +++
target/i386/cpu.h | 12 +++
2 files changed, 67 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8a11470507..e98780773c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1002,6 +1002,45 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = ~0U,
},
+[FEAT_1D_1_EAX] = {
+.type = CPUID_FEATURE_WORD,
+.cpuid = {
+.eax = 0x1D,
+.needs_ecx = true, .ecx = 1,
+.reg = R_EAX,
+},
+.migratable_flags = CPUID_AMX_PALETTE_1_TOTAL_TILE_BYTES_MASK |
+CPUID_AMX_PALETTE_1_BYTES_PER_TILE_MASK,
+},
+[FEAT_1D_1_EBX] = {
+.type = CPUID_FEATURE_WORD,
+.cpuid = {
+.eax = 0x1D,
+.needs_ecx = true, .ecx = 1,
+.reg = R_EBX,
+},
+.migratable_flags = CPUID_AMX_PALETTE_1_BYTES_PER_ROW_MASK |
+CPUID_AMX_PALETTE_1_MAX_NAMES_MASK,
+},
+[FEAT_1D_1_ECX] = {
+.type = CPUID_FEATURE_WORD,
+.cpuid = {
+.eax = 0x1D,
+.needs_ecx = true, .ecx = 1,
+.reg = R_ECX,
+},
+.migratable_flags = CPUID_AMX_PALETTE_1_MAX_ROWS_MASK,
+},
+[FEAT_1E_0_EBX] = {
+.type = CPUID_FEATURE_WORD,
+.cpuid = {
+.eax = 0x1E,
+.needs_ecx = true, .ecx = 0,
+.reg = R_EBX,
+},
+.migratable_flags = CPUID_AMX_TMUL_MAX_K_MASK |
+CPUID_AMX_TMUL_MAX_N_MASK,
+},
/*Below are MSR exposed features*/
[FEAT_ARCH_CAPABILITIES] = {
.type = MSR_FEATURE_WORD,
@@ -1371,6 +1410,22 @@ static FeatureDep feature_dependencies[] = {
.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
.to = { FEAT_14_0_ECX, ~0ull },
},
+{
+.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE },
+.to = { FEAT_1D_1_EAX, ~0ull },
+},
+{
+.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE },
+.to = { FEAT_1D_1_EBX, ~0ull },
+},
+{
+.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE },
+.to = { FEAT_1D_1_ECX, ~0ull },
+},
+{
+.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE },
+.to = { FEAT_1E_0_EBX, ~0ull },
+},
{
.from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
.to = { FEAT_VMX_SECONDARY_CTLS,VMX_SECONDARY_EXEC_RDTSCP },
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7edf5dfac3..1c90fb6c9d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -583,6 +583,14 @@ typedef enum X86Seg {
XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
XSTATE_XTILE_CFG_MASK |
XSTATE_XTILE_DATA_MASK)
+#define CPUID_AMX_PALETTE_1_TOTAL_TILE_BYTES_MASK 0xU
+#define CPUID_AMX_PALETTE_1_BYTES_PER_TILE_MASK (0xU << 16)
+#define CPUID_AMX_PALETTE_1_BYTES_PER_ROW_MASK0xU
+#define CPUID_AMX_PALETTE_1_MAX_NAMES_MASK(0xU << 16)
+#define CPUID_AMX_PALETTE_1_MAX_ROWS_MASK 0xU
+#define CPUID_AMX_TMUL_MAX_K_MASK 0xffU
+#define CPUID_AMX_TMUL_MAX_N_MASK (0xU << 8)
+
/* CPUID feature words */
typedef enum FeatureWord {
FEAT_1_EDX, /* CPUID[1].EDX */
@@ -603,6 +611,10 @@ typedef enum FeatureWord {
FEAT_6_EAX, /* CPUID[6].EAX */
FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
+FEAT_1D_1_EAX, /* CPUID[EAX=0x1d,ECX=1].EAX */
+FEAT_1D_1_EBX, /* CPUID[EAX=0x1d,ECX=1].EBX */
+FEAT_1D_1_ECX, /* CPUID[EAX=0x1d,ECX=1].ECX */
+FEAT_1E_0_EBX, /* CPUID[EAX=0x1e,ECX=0].EBX */
FEAT_ARCH_CAPABILITIES,
FEAT_CORE_CAPABILITY,
FEAT_PERF_CAPABILITIES,
--
2.34.1
