Re: [PATCH v2 3/7] target/ppc: Fix move-to timebase SPR access permissions

2023-11-23 Thread Cédric Le Goater 

On 11/24/23 07:39, Nicholas Piggin wrote:

The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.

Signed-off-by: Nicholas Piggin 



Reviewed-by: Cédric Le Goater 

Thanks,

C.



---
  target/ppc/helper_regs.c | 31 +++
  1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 6f190ab13b..f1493ddca0 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -468,18 +468,33 @@ void register_generic_sprs(PowerPCCPU *cpu)
   _read_tbl, SPR_NOACCESS,
   _read_tbl, SPR_NOACCESS,
   0x);
-spr_register(env, SPR_WR_TBL, "TBL",
- _read_tbl, SPR_NOACCESS,
- _read_tbl, _write_tbl,
- 0x);
  spr_register(env, SPR_TBU, "TBU",
   _read_tbu, SPR_NOACCESS,
   _read_tbu, SPR_NOACCESS,
   0x);
-spr_register(env, SPR_WR_TBU, "TBU",
- _read_tbu, SPR_NOACCESS,
- _read_tbu, _write_tbu,
- 0x);
+#ifndef CONFIG_USER_ONLY
+if (env->has_hv_mode) {
+spr_register_hv(env, SPR_WR_TBL, "TBL",
+SPR_NOACCESS, SPR_NOACCESS,
+SPR_NOACCESS, SPR_NOACCESS,
+SPR_NOACCESS, _write_tbl,
+0x);
+spr_register_hv(env, SPR_WR_TBU, "TBU",
+SPR_NOACCESS, SPR_NOACCESS,
+SPR_NOACCESS, SPR_NOACCESS,
+SPR_NOACCESS, _write_tbu,
+0x);
+} else {
+spr_register(env, SPR_WR_TBL, "TBL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, _write_tbl,
+ 0x);
+spr_register(env, SPR_WR_TBU, "TBU",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, _write_tbu,
+ 0x);
+}
+#endif
  }
  
  void register_non_embedded_sprs(CPUPPCState *env)

[PATCH v2 3/7] target/ppc: Fix move-to timebase SPR access permissions

2023-11-23 Thread Nicholas Piggin 
The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.

Signed-off-by: Nicholas Piggin 
---
 target/ppc/helper_regs.c | 31 +++
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 6f190ab13b..f1493ddca0 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -468,18 +468,33 @@ void register_generic_sprs(PowerPCCPU *cpu)
  _read_tbl, SPR_NOACCESS,
  _read_tbl, SPR_NOACCESS,
  0x);
-spr_register(env, SPR_WR_TBL, "TBL",
- _read_tbl, SPR_NOACCESS,
- _read_tbl, _write_tbl,
- 0x);
 spr_register(env, SPR_TBU, "TBU",
  _read_tbu, SPR_NOACCESS,
  _read_tbu, SPR_NOACCESS,
  0x);
-spr_register(env, SPR_WR_TBU, "TBU",
- _read_tbu, SPR_NOACCESS,
- _read_tbu, _write_tbu,
- 0x);
+#ifndef CONFIG_USER_ONLY
+if (env->has_hv_mode) {
+spr_register_hv(env, SPR_WR_TBL, "TBL",
+SPR_NOACCESS, SPR_NOACCESS,
+SPR_NOACCESS, SPR_NOACCESS,
+SPR_NOACCESS, _write_tbl,
+0x);
+spr_register_hv(env, SPR_WR_TBU, "TBU",
+SPR_NOACCESS, SPR_NOACCESS,
+SPR_NOACCESS, SPR_NOACCESS,
+SPR_NOACCESS, _write_tbu,
+0x);
+} else {
+spr_register(env, SPR_WR_TBL, "TBL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, _write_tbl,
+ 0x);
+spr_register(env, SPR_WR_TBU, "TBU",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, _write_tbu,
+ 0x);
+}
+#endif
 }
 
 void register_non_embedded_sprs(CPUPPCState *env)
-- 
2.42.0