Re: [PATCH v2 4/6] hw/misc: Microchip's 25CSM04 SEEPROM model
Hello Chalapathi On 4/9/24 19:56, Chalapathi V wrote: This commit implements a Serial EEPROM utilizing the Serial Peripheral Interface (SPI) compatible bus. Currently implemented SEEPROM is Microchip's 25CSM04 which provides 4 Mbits of Serial EEPROM utilizing the Serial Peripheral Interface (SPI) compatible bus. The device is organized as 524288 bytes of 8 bits each (512Kbyte) and is optimized for use in consumer and industrial applications where reliable and dependable nonvolatile memory storage is essential. This seeprom device is created from a parent "ssi-peripheral". Can the hw/block/m25p80c model be extented instead ? Thanks, C. Signed-off-by: Chalapathi V --- include/hw/misc/seeprom_25csm04.h | 48 ++ hw/misc/seeprom_25csm04.c | 780 ++ hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/ppc/Kconfig| 1 + 5 files changed, 833 insertions(+) create mode 100644 include/hw/misc/seeprom_25csm04.h create mode 100644 hw/misc/seeprom_25csm04.c diff --git a/include/hw/misc/seeprom_25csm04.h b/include/hw/misc/seeprom_25csm04.h new file mode 100644 index 00..0343530354 --- /dev/null +++ b/include/hw/misc/seeprom_25csm04.h @@ -0,0 +1,48 @@ +/* + * 25CSM04 Serial EEPROM model + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * The Microchip Technology Inc. 25CSM04 provides 4 Mbits of Serial EEPROM + * utilizing the Serial Peripheral Interface (SPI) compatible bus. The device + * is organized as 524288 bytes of 8 bits each (512Kbyte) and is optimized + * for use in consumer and industrial applications where reliable and + * dependable nonvolatile memory storage is essential + */ + +#ifndef SEEPROM_25CSM04_H +#define SEEPROM_25CSM04_H + +#include "hw/ssi/ssi.h" +#include "qom/object.h" + +#define TYPE_SEEPROM_25CSM04 "seeprom-25csm04" + +OBJECT_DECLARE_SIMPLE_TYPE(SeepromCsm04, SEEPROM_25CSM04) + +typedef struct SeepromCsm04 { +SSIPeripheral parent_object; + +char*file; +char*file_name; +uint8_t opcode; +uint32_taddr; +uint8_t rd_state; +boollocked; +boolcommand_byte; +/* device registers */ +uint8_t status0; +uint8_t status1; +uint8_t dsn[16]; +uint8_t uplid[256]; +uint8_t mpr[8]; +uint8_t idr[5]; +} SeepromCsm04; + +uint32_t seeprom_transfer(SSIPeripheral *ss, uint32_t tx); +void seeprom_realize(SSIPeripheral *dev, Error **errp); +bool compute_addr(SeepromCsm04 *s, uint32_t tx); +bool validate_addr(SeepromCsm04 *s); +#endif /* PPC_PNV_SPI_SEEPROM_H */ diff --git a/hw/misc/seeprom_25csm04.c b/hw/misc/seeprom_25csm04.c new file mode 100644 index 00..45df66e4b0 --- /dev/null +++ b/hw/misc/seeprom_25csm04.c @@ -0,0 +1,780 @@ +/* + * 25CSM04 Serial EEPROM model + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/misc/seeprom_25csm04.h" +#include "hw/qdev-properties.h" +#include "qemu/datadir.h" +#include + +#define SPI_DEBUG(x) + +/* + * 2-byte STATUS register which is a combination of six nonvolatile bits of + * EEPROM and five volatile latches. + * + * status 0: + * bit 7 WPEN: Write-Protect Enable bit + * 1 = Write-Protect pin is enabled, 0 = Write-Protect pin is ignored + * + * bit 3-2 BP<1:0>: Block Protection bits + * 00 = No array write protection + * 01 = Upper quarter memory array protection + * 10 = Upper half memory array protection + * 11 = Entire memory array protection + * + * bit 1 WEL: Write Enable Latch bit + * 1 = WREN has been executed and device is enabled for writing + * 0 = Device is not write-enabled + * + * bit 0 RDY/BSY: Ready/Busy Status Latch bit + * 1 = Device is busy with an internal write cycle + * 0 = Device is ready for a new sequence + */ +#define STATUS0_WPEN0x7 +#define STATUS0_BP 0x2 +#define STATUS0_WEL 0x1 +#define STATUS0_BUSY0x0 + +/* + * status 1: + * bit 7 WPM: Write Protection Mode bit(1) + * 1 = Enhanced Write Protection mode selected (factory default) + * 0 = Legacy Write Protection mode selected + * + * bit 6 ECS: Error Correction State Latch bit + * 1 = The previously executed read sequence did require the ECC + * 0 = The previous executed read sequence did not require the ECC + * + * bit 5 FMPC: Freeze Memory Protection Configuration bit(2) + * 1 = Memory Partition registers and write protection mode are permanently + * frozen and cannot be modified + * 0 = Memory Partition registers and write protection mode are not frozen + * and are modifiable + * + * bit 4 PREL: Partition Register Write Enable Latch bit + * 1 = PRWE has been executed and WMPR, FRZR and PPAB instructions are enabled + * 0 = WMPR, FRZR and PPAB instructions are disabled + * + * bit 3 PABP: Partition Address Boundary Protection bit + *
[PATCH v2 4/6] hw/misc: Microchip's 25CSM04 SEEPROM model
This commit implements a Serial EEPROM utilizing the Serial Peripheral Interface (SPI) compatible bus. Currently implemented SEEPROM is Microchip's 25CSM04 which provides 4 Mbits of Serial EEPROM utilizing the Serial Peripheral Interface (SPI) compatible bus. The device is organized as 524288 bytes of 8 bits each (512Kbyte) and is optimized for use in consumer and industrial applications where reliable and dependable nonvolatile memory storage is essential. This seeprom device is created from a parent "ssi-peripheral". Signed-off-by: Chalapathi V --- include/hw/misc/seeprom_25csm04.h | 48 ++ hw/misc/seeprom_25csm04.c | 780 ++ hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/ppc/Kconfig| 1 + 5 files changed, 833 insertions(+) create mode 100644 include/hw/misc/seeprom_25csm04.h create mode 100644 hw/misc/seeprom_25csm04.c diff --git a/include/hw/misc/seeprom_25csm04.h b/include/hw/misc/seeprom_25csm04.h new file mode 100644 index 00..0343530354 --- /dev/null +++ b/include/hw/misc/seeprom_25csm04.h @@ -0,0 +1,48 @@ +/* + * 25CSM04 Serial EEPROM model + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * The Microchip Technology Inc. 25CSM04 provides 4 Mbits of Serial EEPROM + * utilizing the Serial Peripheral Interface (SPI) compatible bus. The device + * is organized as 524288 bytes of 8 bits each (512Kbyte) and is optimized + * for use in consumer and industrial applications where reliable and + * dependable nonvolatile memory storage is essential + */ + +#ifndef SEEPROM_25CSM04_H +#define SEEPROM_25CSM04_H + +#include "hw/ssi/ssi.h" +#include "qom/object.h" + +#define TYPE_SEEPROM_25CSM04 "seeprom-25csm04" + +OBJECT_DECLARE_SIMPLE_TYPE(SeepromCsm04, SEEPROM_25CSM04) + +typedef struct SeepromCsm04 { +SSIPeripheral parent_object; + +char*file; +char*file_name; +uint8_t opcode; +uint32_taddr; +uint8_t rd_state; +boollocked; +boolcommand_byte; +/* device registers */ +uint8_t status0; +uint8_t status1; +uint8_t dsn[16]; +uint8_t uplid[256]; +uint8_t mpr[8]; +uint8_t idr[5]; +} SeepromCsm04; + +uint32_t seeprom_transfer(SSIPeripheral *ss, uint32_t tx); +void seeprom_realize(SSIPeripheral *dev, Error **errp); +bool compute_addr(SeepromCsm04 *s, uint32_t tx); +bool validate_addr(SeepromCsm04 *s); +#endif /* PPC_PNV_SPI_SEEPROM_H */ diff --git a/hw/misc/seeprom_25csm04.c b/hw/misc/seeprom_25csm04.c new file mode 100644 index 00..45df66e4b0 --- /dev/null +++ b/hw/misc/seeprom_25csm04.c @@ -0,0 +1,780 @@ +/* + * 25CSM04 Serial EEPROM model + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/misc/seeprom_25csm04.h" +#include "hw/qdev-properties.h" +#include "qemu/datadir.h" +#include + +#define SPI_DEBUG(x) + +/* + * 2-byte STATUS register which is a combination of six nonvolatile bits of + * EEPROM and five volatile latches. + * + * status 0: + * bit 7 WPEN: Write-Protect Enable bit + * 1 = Write-Protect pin is enabled, 0 = Write-Protect pin is ignored + * + * bit 3-2 BP<1:0>: Block Protection bits + * 00 = No array write protection + * 01 = Upper quarter memory array protection + * 10 = Upper half memory array protection + * 11 = Entire memory array protection + * + * bit 1 WEL: Write Enable Latch bit + * 1 = WREN has been executed and device is enabled for writing + * 0 = Device is not write-enabled + * + * bit 0 RDY/BSY: Ready/Busy Status Latch bit + * 1 = Device is busy with an internal write cycle + * 0 = Device is ready for a new sequence + */ +#define STATUS0_WPEN0x7 +#define STATUS0_BP 0x2 +#define STATUS0_WEL 0x1 +#define STATUS0_BUSY0x0 + +/* + * status 1: + * bit 7 WPM: Write Protection Mode bit(1) + * 1 = Enhanced Write Protection mode selected (factory default) + * 0 = Legacy Write Protection mode selected + * + * bit 6 ECS: Error Correction State Latch bit + * 1 = The previously executed read sequence did require the ECC + * 0 = The previous executed read sequence did not require the ECC + * + * bit 5 FMPC: Freeze Memory Protection Configuration bit(2) + * 1 = Memory Partition registers and write protection mode are permanently + * frozen and cannot be modified + * 0 = Memory Partition registers and write protection mode are not frozen + * and are modifiable + * + * bit 4 PREL: Partition Register Write Enable Latch bit + * 1 = PRWE has been executed and WMPR, FRZR and PPAB instructions are enabled + * 0 = WMPR, FRZR and PPAB instructions are disabled + * + * bit 3 PABP: Partition Address Boundary Protection bit + * 1 = Partition Address Endpoints set in Memory Partition registers + * cannot be modified + * 0 = Partition Address Endpoints set in Memo