Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 5
target/arm/tcg/translate-a64.c | 51 +-
2 files changed, 25 insertions(+), 31 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 07b604ec30..3ea0643370 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -926,6 +926,8 @@ SABD_v 0.00 1110 ..1 . 01110 1 . .
@qrrr_e
UABD_v 0.10 1110 ..1 . 01110 1 . . @qrrr_e
SABA_v 0.00 1110 ..1 . 0 1 . . @qrrr_e
UABA_v 0.10 1110 ..1 . 0 1 . . @qrrr_e
+MUL_v 0.00 1110 ..1 . 10011 1 . . @qrrr_e
+PMUL_v 0.10 1110 001 . 10011 1 . . @qrrr_b
### Advanced SIMD scalar x indexed element
@@ -967,3 +969,6 @@ FMLAL_vi0.00 10 .. . 0 . .
@qrrx_h
FMLSL_vi0.00 10 .. 0100 . 0 . . @qrrx_h
FMLAL2_vi 0.10 10 .. 1000 . 0 . . @qrrx_h
FMLSL2_vi 0.10 10 .. 1100 . 0 . . @qrrx_h
+
+MUL_vi 0.00 01 .. 1000 . 0 . . @qrrx_h
+MUL_vi 0.00 10 . . 1000 . 0 . . @qrrx_s
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 61afbc434f..1909d1426c 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5468,6 +5468,8 @@ TRANS(SABA_v, do_gvec_fn3_no64, a, gen_gvec_saba)
TRANS(UABA_v, do_gvec_fn3_no64, a, gen_gvec_uaba)
TRANS(SABD_v, do_gvec_fn3_no64, a, gen_gvec_sabd)
TRANS(UABD_v, do_gvec_fn3_no64, a, gen_gvec_uabd)
+TRANS(MUL_v, do_gvec_fn3_no64, a, tcg_gen_gvec_mul)
+TRANS(PMUL_v, do_gvec_op3_ool, a, 0, gen_helper_gvec_pmul_b)
static bool do_cmop_v(DisasContext *s, arg_qrrr_e *a, TCGCond cond)
{
@@ -5694,6 +5696,22 @@ TRANS_FEAT(FMLSL_vi, aa64_fhm, do_fmlal_idx, a, true,
false)
TRANS_FEAT(FMLAL2_vi, aa64_fhm, do_fmlal_idx, a, false, true)
TRANS_FEAT(FMLSL2_vi, aa64_fhm, do_fmlal_idx, a, true, true)
+static bool do_int3_vector_idx(DisasContext *s, arg_qrrx_e *a,
+ gen_helper_gvec_3 * const fns[2])
+{
+assert(a->esz == MO_16 || a->esz == MO_32);
+if (fp_access_check(s)) {
+gen_gvec_op3_ool(s, a->q, a->rd, a->rn, a->rm, a->idx, fns[a->esz -
1]);
+}
+return true;
+}
+
+static gen_helper_gvec_3 * const f_vector_idx_mul[2] = {
+gen_helper_gvec_mul_idx_h,
+gen_helper_gvec_mul_idx_s,
+};
+TRANS(MUL_vi, do_int3_vector_idx, a, f_vector_idx_mul)
+
/*
* Advanced SIMD scalar pairwise
*/
@@ -10927,12 +10945,6 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
int rd = extract32(insn, 0, 5);
switch (opcode) {
-case 0x13: /* MUL, PMUL */
-if (u && size != 0) {
-unallocated_encoding(s);
-return;
-}
-/* fall through */
case 0x12: /* MLA, MLS */
if (size == 3) {
unallocated_encoding(s);
@@ -10969,6 +10981,7 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
case 0x0f: /* SABA, UABA */
case 0x10: /* ADD, SUB */
case 0x11: /* CMTST, CMEQ */
+case 0x13: /* MUL, PMUL */
unallocated_encoding(s);
return;
}
@@ -10978,13 +10991,6 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
}
switch (opcode) {
-case 0x13: /* MUL, PMUL */
-if (!u) { /* MUL */
-gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size);
-} else { /* PMUL */
-gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, gen_helper_gvec_pmul_b);
-}
-return;
case 0x12: /* MLA, MLS */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mls, size);
@@ -12198,7 +12204,6 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
TCGv_ptr fpst;
switch (16 * u + opcode) {
-case 0x08: /* MUL */
case 0x10: /* MLA */
case 0x14: /* MLS */
if (is_scalar) {
@@ -12285,6 +12290,7 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
case 0x01: /* FMLA */
case 0x04: /* FMLSL */
case 0x05: /* FMLS */
+case 0x08: /* MUL */
case 0x09: /* FMUL */
case 0x18: /* FMLAL2 */
case 0x19: /* FMULX */
@@ -12407,22 +12413,6 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
}
return;
-case 0x08: /* MUL */
-if (!is_long && !is_scalar) {
-static gen_helper_gvec_3 * const fns[3] = {
-gen_helper_gvec_mul_idx_h,
-gen_helper_gvec_mul_idx_s,
-gen_helper_gvec_mul_idx_d,
-};
-tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
- vec_full_reg_offset(s, rn),
- vec_full_reg_offset(s, rm),
- is_q ? 16 : 8, vec_full_reg_size(s),
-
