RE: [PATCH v3 09/12] target/hexagon: import lexer for idef-parser

[Taylor Simpson]

>From: Paolo Montesel  
>Sent: Wednesday, April 28, 2021 5:41 AM
>To: Taylor Simpson 
>Cc: Alessandro Di Federico ; qemu-devel@nongnu.org; Brian 
>Cain ; ni...@rev.ng; >phi...@redhat.com; 
>richard.hender...@linaro.org; Alessandro Di Federico 
>Subject: Re: [PATCH v3 09/12] target/hexagon: import lexer for idef-parser
>
>> +"fLSBNEW(P"{LOWER_PRE}"N)" { yylval->rvalue.type = PREDICATE;
>> +                           yylval->http://rvalue.pre.id = yytext[9];
>> +                           yylval->rvalue.bit_width = 32;
>> +                           yylval->rvalue.is_dotnew = true;
>> +                           return PRE; }
>> +"fLSBNEW0"               { yylval->rvalue.type = PREDICATE;
>> +                           yylval->http://rvalue.pre.id = '0';
>> +                           yylval->rvalue.bit_width = 32;
>> +                           yylval->rvalue.is_dotnew = true;
>> +                           return PRE; }
>> +"fLSBNEW1"               { yylval->rvalue.type = PREDICATE;
>> +                           yylval->http://rvalue.pre.id = '1';
>> +                           yylval->rvalue.bit_width = 32;
>> +                           yylval->rvalue.is_dotnew = true;
>> +                           return PRE; }
>> +"fLSBNEW1NOT"            { yylval->rvalue.type = PREDICATE;
>> +                           yylval->http://rvalue.pre.id = '1';
>> +                           yylval->rvalue.bit_width = 32;
>> +                           yylval->rvalue.is_dotnew = true;
>> +                           return PRE; }
>
>These represent the least significant bit of the operand.  Perhaps you should 
>set the bit_width to 1?  Or do tcg_gen_andi_tl(..., 1)?
>
>What I ended up doing is reworking how LSB* are handled.
>Now there's a special token `LSBNEW` that's implemented as a `tcg_gen_andi` in 
>the parser, and it's used only for `fLSBNEW`.
>The other cases are expanded in the preprocessing part like this:
>
>/* Least significant bit operations */
>#define fLSBNEW0 fLSBNEW(P0N)
>#define fLSBNEW1 fLSBNEW(P1N)
>#define fLSBOLDNOT(VAL) fGETBIT(0, ~VAL)
>#define fLSBNEWNOT(PRED) (fLSBNEW(~PRED))
>#define fLSBNEW0NOT fLSBNEW(~P0N)
>#define fLSBNEW1NOT fLSBNEW(~P1N)
>
>Let me know what you think.
>
>~Paolo

That should work.


Taylor

Re: [PATCH v3 09/12] target/hexagon: import lexer for idef-parser

[Paolo Montesel]

>
> > +"fLSBNEW(P"{LOWER_PRE}"N)" { yylval->rvalue.type = PREDICATE;
> > +   yylval->rvalue.pre.id = yytext[9];
> > +   yylval->rvalue.bit_width = 32;
> > +   yylval->rvalue.is_dotnew = true;
> > +   return PRE; }
> > +"fLSBNEW0"   { yylval->rvalue.type = PREDICATE;
> > +   yylval->rvalue.pre.id = '0';
> > +   yylval->rvalue.bit_width = 32;
> > +   yylval->rvalue.is_dotnew = true;
> > +   return PRE; }
> > +"fLSBNEW1"   { yylval->rvalue.type = PREDICATE;
> > +   yylval->rvalue.pre.id = '1';
> > +   yylval->rvalue.bit_width = 32;
> > +   yylval->rvalue.is_dotnew = true;
> > +   return PRE; }
> > +"fLSBNEW1NOT"{ yylval->rvalue.type = PREDICATE;
> > +   yylval->rvalue.pre.id = '1';
> > +   yylval->rvalue.bit_width = 32;
> > +   yylval->rvalue.is_dotnew = true;
> > +   return PRE; }
>
> These represent the least significant bit of the operand.  Perhaps you
> should set the bit_width to 1?  Or do tcg_gen_andi_tl(..., 1)?
>

What I ended up doing is reworking how LSB* are handled.
Now there's a special token `LSBNEW` that's implemented as a `tcg_gen_andi`
in the parser, and it's used only for `fLSBNEW`.
The other cases are expanded in the preprocessing part like this:

/* Least significant bit operations */
#define fLSBNEW0 fLSBNEW(P0N)
#define fLSBNEW1 fLSBNEW(P1N)
#define fLSBOLDNOT(VAL) fGETBIT(0, ~VAL)
#define fLSBNEWNOT(PRED) (fLSBNEW(~PRED))
#define fLSBNEW0NOT fLSBNEW(~P0N)
#define fLSBNEW1NOT fLSBNEW(~P1N)

Let me know what you think.

~Paolo

RE: [PATCH v3 09/12] target/hexagon: import lexer for idef-parser

[Taylor Simpson]

> -Original Message-
> From: Alessandro Di Federico 
> Sent: Tuesday, March 30, 2021 9:38 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; bab...@rev.ng; ni...@rev.ng; phi...@redhat.com;
> richard.hender...@linaro.org; Alessandro Di Federico 
> Subject: [PATCH v3 09/12] target/hexagon: import lexer for idef-parser
> 

> +"fLSBNEW(P"{LOWER_PRE}"N)" { yylval->rvalue.type = PREDICATE;
> +   yylval->rvalue.pre.id = yytext[9];
> +   yylval->rvalue.bit_width = 32;
> +   yylval->rvalue.is_dotnew = true;
> +   return PRE; }
> +"fLSBNEW0"   { yylval->rvalue.type = PREDICATE;
> +   yylval->rvalue.pre.id = '0';
> +   yylval->rvalue.bit_width = 32;
> +   yylval->rvalue.is_dotnew = true;
> +   return PRE; }
> +"fLSBNEW1"   { yylval->rvalue.type = PREDICATE;
> +   yylval->rvalue.pre.id = '1';
> +   yylval->rvalue.bit_width = 32;
> +   yylval->rvalue.is_dotnew = true;
> +   return PRE; }
> +"fLSBNEW1NOT"{ yylval->rvalue.type = PREDICATE;
> +   yylval->rvalue.pre.id = '1';
> +   yylval->rvalue.bit_width = 32;
> +   yylval->rvalue.is_dotnew = true;
> +   return PRE; }

These represent the least significant bit of the operand.  Perhaps you should 
set the bit_width to 1?  Or do tcg_gen_andi_tl(..., 1)?

Thanks,
Taylor

[PATCH v3 09/12] target/hexagon: import lexer for idef-parser

[Alessandro Di Federico via]

From: Paolo Montesel 

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Paolo Montesel 
---
 target/hexagon/idef-parser/idef-parser.h  | 240 +++
 target/hexagon/idef-parser/idef-parser.lex| 611 ++
 target/hexagon/meson.build|   4 +
 tests/docker/dockerfiles/alpine.docker|   1 +
 tests/docker/dockerfiles/centos7.docker   |   1 +
 tests/docker/dockerfiles/centos8.docker   |   1 +
 tests/docker/dockerfiles/debian10.docker  |   1 +
 .../dockerfiles/fedora-i386-cross.docker  |   1 +
 .../dockerfiles/fedora-win32-cross.docker |   1 +
 .../dockerfiles/fedora-win64-cross.docker |   1 +
 tests/docker/dockerfiles/fedora.docker|   1 +
 tests/docker/dockerfiles/opensuse-leap.docker |   1 +
 tests/docker/dockerfiles/ubuntu.docker|   1 +
 tests/docker/dockerfiles/ubuntu1804.docker|   1 +
 tests/docker/dockerfiles/ubuntu2004.docker|   3 +-
 15 files changed, 868 insertions(+), 1 deletion(-)
 create mode 100644 target/hexagon/idef-parser/idef-parser.h
 create mode 100644 target/hexagon/idef-parser/idef-parser.lex

diff --git a/target/hexagon/idef-parser/idef-parser.h 
b/target/hexagon/idef-parser/idef-parser.h
new file mode 100644
index 00..ecfa0174e2
--- /dev/null
+++ b/target/hexagon/idef-parser/idef-parser.h
@@ -0,0 +1,240 @@
+/*
+ * Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#ifndef IDEF_PARSER_H
+#define IDEF_PARSER_H
+
+#include 
+#include 
+#include 
+#include 
+
+#define TCGV_NAME_SIZE 7
+#define MAX_WRITTEN_REGS 32
+#define OFFSET_STR_LEN 32
+#define ALLOC_LIST_LEN 32
+#define ALLOC_NAME_SIZE 32
+#define INIT_LIST_LEN 32
+#define OUT_BUF_LEN (1024 * 1024)
+#define SIGNATURE_BUF_LEN (128 * 1024)
+#define HEADER_BUF_LEN (128 * 1024)
+
+/* Variadic macros to wrap the buffer printing functions */
+#define EMIT(c, ...) \
+do { \
+g_string_append_printf((c)->out_str, __VA_ARGS__);   \
+} while (0)
+
+#define EMIT_SIG(c, ...)   
\
+do {   
\
+g_string_append_printf((c)->signature_str, __VA_ARGS__);   
\
+} while (0)
+
+#define EMIT_HEAD(c, ...)  
\
+do {   
\
+g_string_append_printf((c)->header_str, __VA_ARGS__);  
\
+} while (0)
+
+/**
+ * Type of register, assigned to the HexReg.type field
+ */
+typedef enum {GENERAL_PURPOSE, CONTROL, MODIFIER, DOTNEW} RegType;
+
+/**
+ * Types of control registers, assigned to the HexReg.id field
+ */
+typedef enum {SP, FP, LR, GP, LC0, LC1, SA0, SA1} CregType;
+
+/**
+ * Identifier string of the control registers, indexed by the CregType enum
+ */
+extern const char *creg_str[];
+
+/**
+ * Semantic record of the REG tokens, identifying registers
+ */
+typedef struct HexReg {
+CregType id;/**< Identifier of the register  */
+RegType type;   /**< Type of the register*/
+unsigned bit_width; /**< Bit width of the reg, 32 or 64 bits */
+} HexReg;
+
+/**
+ * Data structure, identifying a TCGv temporary value
+ */
+typedef struct HexTmp {
+int index;  /**< Index of the TCGv temporary value*/
+} HexTmp;
+
+/**
+ * Enum of the possible immediated, an immediate is a value which is known
+ * at tinycode generation time, e.g. an integer value, not a TCGv
+ */
+enum ImmUnionTag {I, VARIABLE, VALUE, QEMU_TMP, IMM_PC, IMM_CONSTEXT};
+
+/**
+ * Semantic record of the IMM token, identifying an immediate constant
+ */
+typedef struct HexImm {
+union {
+char id;/**< Identifier of the immediate */
+uint64_t value; /**< Immediate value (for VALUE type immediates) */
+uint64_t index; /**< Index of the immediate (for int temp vars)  */
+};
+enum ImmUnionTag type;  /**< Type of the immediate  */
+} HexImm;
+
+/**
+ * Semantic record of the PRE token, identifying a predicate
+ */
+typedef stru