RE: [PATCH v3 12/16] aspeed/soc: Add AST2700 support
Hi Cerdric,
> On 4/19/24 09:58, Jamin Lin wrote:
> > Hi Cedric,
> >> On 4/16/24 11:18, Jamin Lin wrote:
> >>> Initial definitions for a simple machine using an AST2700 SOC
> >>> (Cortex-a35
> >> CPU).
> >>>
> >>> AST2700 SOC and its interrupt controller are too complex to handle
> >>> in the common Aspeed SoC framework. We introduce a new ast2700 class
> >>> with instance_init and realize handlers.
> >>>
> >>> AST2700 is a 64 bits quad core cpus and support 8 watchdog.
> >>> Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to
> 8.
> >>> In addition, update AspeedSocState to support scuio, sli, sliio and intc.
> >>>
> >>> Add TYPE_ASPEED27X0_SOC machine type.
> >>>
> >>> The SDMC controller is unlocked at SPL stage.
> >>> At present, only supports to emulate booting start from u-boot stage.
> >>> Set SDMC controller unlocked by default.
> >>>
> >>> In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
> >>> It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to
> 136.
> >>> And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is
> >>> connected to GICINT or-gates instead of GIC device.
> >>>
> >>> Signed-off-by: Troy Lee
> >>> Signed-off-by: Jamin Lin
> >>
> >> Before I forget, please see a little comment below regarding user
> >> creatable devices.
> >>
> >> The model looks fine. The interrupt controller part is more complex
> >> than the previous SoCs so I will come back to it later when I have more
> time.
> > Thanks for your kindly support.
> >>> ---
> >>>hw/arm/aspeed_ast27x0.c | 554
> >>
> >>>hw/arm/meson.build | 1 +
> >>>include/hw/arm/aspeed_soc.h | 26 +-
> >>>3 files changed, 579 insertions(+), 2 deletions(-)
> >>>create mode 100644 hw/arm/aspeed_ast27x0.c
> >>>
> >>> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c new
> >>> file mode 100644 index 00..754c963230
> >>> --- /dev/null
> >>> +++ b/hw/arm/aspeed_ast27x0.c
> >>> @@ -0,0 +1,554 @@
> >>> +/*
> >>> + * ASPEED SoC 27x0 family
> >>> + *
> >>> + * Copyright (C) 2024 ASPEED Technology Inc.
> >>> + *
> >>> + * This code is licensed under the GPL version 2 or later. See
> >>> + * the COPYING file in the top-level directory.
> >>> + *
> >>> + * Implementation extracted from the AST2600 and adapted for AST27x0.
> >>> + */
> >>> +
> >>> +#include "qemu/osdep.h"
> >>> +#include "qapi/error.h"
> >>> +#include "hw/misc/unimp.h"
> >>> +#include "hw/arm/aspeed_soc.h"
> >>> +#include "qemu/module.h"
> >>> +#include "qemu/error-report.h"
> >>> +#include "hw/i2c/aspeed_i2c.h"
> >>> +#include "net/net.h"
> >>> +#include "sysemu/sysemu.h"
> >>> +#include "hw/intc/arm_gicv3.h"
> >>> +#include "qapi/qmp/qlist.h"
> >>> +
> >>> +static const hwaddr aspeed_soc_ast2700_memmap[] = {
> >>> +[ASPEED_DEV_SPI_BOOT] = 0x4,
> >>> +[ASPEED_DEV_SRAM] = 0x1000,
> >>> +[ASPEED_DEV_SDMC] = 0x12C0,
> >>> +[ASPEED_DEV_SCU] = 0x12C02000,
> >>> +[ASPEED_DEV_SCUIO] = 0x14C02000,
> >>> +[ASPEED_DEV_UART0] = 0X14C33000,
> >>> +[ASPEED_DEV_UART1] = 0X14C33100,
> >>> +[ASPEED_DEV_UART2] = 0X14C33200,
> >>> +[ASPEED_DEV_UART3] = 0X14C33300,
> >>> +[ASPEED_DEV_UART4] = 0X12C1A000,
> >>> +[ASPEED_DEV_UART5] = 0X14C33400,
> >>> +[ASPEED_DEV_UART6] = 0X14C33500,
> >>> +[ASPEED_DEV_UART7] = 0X14C33600,
> >>> +[ASPEED_DEV_UART8] = 0X14C33700,
> >>> +[ASPEED_DEV_UART9] = 0X14C33800,
> >>> +[ASPEED_DEV_UART10]= 0X14C33900,
> >>> +[ASPEED_DEV_UART11]= 0X14C33A00,
> >>> +[ASPEED_DEV_UART12]= 0X14C33B00,
> >>> +[ASPEED_DEV_WDT] = 0x14C37000,
> >>> +[ASPEED_DEV_VUART] = 0X14C3,
> >>> +[ASPEED_DEV_FMC] = 0x1400,
> >>> +[ASPEED_DEV_SPI0] = 0x1401,
> >>> +[ASPEED_DEV_SPI1] = 0x1402,
> >>> +[ASPEED_DEV_SPI2] = 0x1403,
> >>> +[ASPEED_DEV_SDRAM] = 0x4,
> >>> +[ASPEED_DEV_MII1] = 0x1404,
> >>> +[ASPEED_DEV_MII2] = 0x14040008,
> >>> +[ASPEED_DEV_MII3] = 0x14040010,
> >>> +[ASPEED_DEV_ETH1] = 0x1405,
> >>> +[ASPEED_DEV_ETH2] = 0x1406,
> >>> +[ASPEED_DEV_ETH3] = 0x1407,
> >>> +[ASPEED_DEV_EMMC] = 0x1209,
> >>> +[ASPEED_DEV_INTC] = 0x1210,
> >>> +[ASPEED_DEV_SLI] = 0x12C17000,
> >>> +[ASPEED_DEV_SLIIO] = 0x14C1E000,
> >>> +[ASPEED_GIC_DIST] = 0x1220,
> >>> +[ASPEED_GIC_REDIST]= 0x1228,
> >>> +};
> >>> +
> >>> +#define AST2700_MAX_IRQ 288
> >>> +
> >>> +/* Shared Peripheral Interrupt values below are offset by -32 from
> >>> +datasheet */ static const int aspeed_soc_ast2700_irqmap[] = {
> >>> +[ASPEED_DEV_UART0] = 132,
> >>> +[ASPEED_DEV_UART1] = 132,
> >>> +[ASPEED_DEV_UART2] = 132,
> >>> +[ASPEED_DEV_UART3] = 132,
Re: [PATCH v3 12/16] aspeed/soc: Add AST2700 support
On 4/19/24 09:58, Jamin Lin wrote:
Hi Cedric,
On 4/16/24 11:18, Jamin Lin wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35
CPU).
AST2700 SOC and its interrupt controller are too complex to handle in
the common Aspeed SoC framework. We introduce a new ast2700 class with
instance_init and realize handlers.
AST2700 is a 64 bits quad core cpus and support 8 watchdog.
Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
In addition, update AspeedSocState to support scuio, sli, sliio and intc.
Add TYPE_ASPEED27X0_SOC machine type.
The SDMC controller is unlocked at SPL stage.
At present, only supports to emulate booting start from u-boot stage.
Set SDMC controller unlocked by default.
In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136.
And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is
connected to GICINT or-gates instead of GIC device.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Before I forget, please see a little comment below regarding user creatable
devices.
The model looks fine. The interrupt controller part is more complex than the
previous SoCs so I will come back to it later when I have more time.
Thanks for your kindly support.
---
hw/arm/aspeed_ast27x0.c | 554
hw/arm/meson.build | 1 +
include/hw/arm/aspeed_soc.h | 26 +-
3 files changed, 579 insertions(+), 2 deletions(-)
create mode 100644 hw/arm/aspeed_ast27x0.c
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c new
file mode 100644 index 00..754c963230
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0.c
@@ -0,0 +1,554 @@
+/*
+ * ASPEED SoC 27x0 family
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Implementation extracted from the AST2600 and adapted for AST27x0.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "hw/i2c/aspeed_i2c.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/arm_gicv3.h"
+#include "qapi/qmp/qlist.h"
+
+static const hwaddr aspeed_soc_ast2700_memmap[] = {
+[ASPEED_DEV_SPI_BOOT] = 0x4,
+[ASPEED_DEV_SRAM] = 0x1000,
+[ASPEED_DEV_SDMC] = 0x12C0,
+[ASPEED_DEV_SCU] = 0x12C02000,
+[ASPEED_DEV_SCUIO] = 0x14C02000,
+[ASPEED_DEV_UART0] = 0X14C33000,
+[ASPEED_DEV_UART1] = 0X14C33100,
+[ASPEED_DEV_UART2] = 0X14C33200,
+[ASPEED_DEV_UART3] = 0X14C33300,
+[ASPEED_DEV_UART4] = 0X12C1A000,
+[ASPEED_DEV_UART5] = 0X14C33400,
+[ASPEED_DEV_UART6] = 0X14C33500,
+[ASPEED_DEV_UART7] = 0X14C33600,
+[ASPEED_DEV_UART8] = 0X14C33700,
+[ASPEED_DEV_UART9] = 0X14C33800,
+[ASPEED_DEV_UART10]= 0X14C33900,
+[ASPEED_DEV_UART11]= 0X14C33A00,
+[ASPEED_DEV_UART12]= 0X14C33B00,
+[ASPEED_DEV_WDT] = 0x14C37000,
+[ASPEED_DEV_VUART] = 0X14C3,
+[ASPEED_DEV_FMC] = 0x1400,
+[ASPEED_DEV_SPI0] = 0x1401,
+[ASPEED_DEV_SPI1] = 0x1402,
+[ASPEED_DEV_SPI2] = 0x1403,
+[ASPEED_DEV_SDRAM] = 0x4,
+[ASPEED_DEV_MII1] = 0x1404,
+[ASPEED_DEV_MII2] = 0x14040008,
+[ASPEED_DEV_MII3] = 0x14040010,
+[ASPEED_DEV_ETH1] = 0x1405,
+[ASPEED_DEV_ETH2] = 0x1406,
+[ASPEED_DEV_ETH3] = 0x1407,
+[ASPEED_DEV_EMMC] = 0x1209,
+[ASPEED_DEV_INTC] = 0x1210,
+[ASPEED_DEV_SLI] = 0x12C17000,
+[ASPEED_DEV_SLIIO] = 0x14C1E000,
+[ASPEED_GIC_DIST] = 0x1220,
+[ASPEED_GIC_REDIST]= 0x1228,
+};
+
+#define AST2700_MAX_IRQ 288
+
+/* Shared Peripheral Interrupt values below are offset by -32 from
+datasheet */ static const int aspeed_soc_ast2700_irqmap[] = {
+[ASPEED_DEV_UART0] = 132,
+[ASPEED_DEV_UART1] = 132,
+[ASPEED_DEV_UART2] = 132,
+[ASPEED_DEV_UART3] = 132,
+[ASPEED_DEV_UART4] = 8,
+[ASPEED_DEV_UART5] = 132,
+[ASPEED_DEV_UART6] = 132,
+[ASPEED_DEV_UART7] = 132,
+[ASPEED_DEV_UART8] = 132,
+[ASPEED_DEV_UART9] = 132,
+[ASPEED_DEV_UART10]= 132,
+[ASPEED_DEV_UART11]= 132,
+[ASPEED_DEV_UART12]= 132,
+[ASPEED_DEV_FMC] = 131,
+[ASPEED_DEV_SDMC] = 0,
+[ASPEED_DEV_SCU] = 12,
+[ASPEED_DEV_ADC] = 130,
+[ASPEED_DEV_XDMA] = 5,
+[ASPEED_DEV_EMMC] = 15,
+[ASPEED_DEV_GPIO] = 11,
+[ASPEED_DEV_GPIO_1_8V] = 130,
+[ASPEED_DEV_RTC] = 13,
+[ASPEED_DEV_TIMER1]= 16,
+[ASPEED_DEV_TIMER2]= 17,
+
Re: [PATCH v3 12/16] aspeed/soc: Add AST2700 support
Peter,
Could you please look at aspeed_soc_ast2700_gic() when you have some time ?
My GIC knowledge is a bit limited and I would feel more confortable with
your feedback.
The rest looks good to me.
Thanks,
C.
On 4/16/24 11:18, Jamin Lin wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
AST2700 is a 64 bits quad core cpus and support 8 watchdog.
Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
In addition, update AspeedSocState to support scuio, sli, sliio and intc.
Add TYPE_ASPEED27X0_SOC machine type.
The SDMC controller is unlocked at SPL stage.
At present, only supports to emulate booting
start from u-boot stage. Set SDMC controller
unlocked by default.
In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136.
And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is connected to
GICINT or-gates instead of GIC device.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 554
hw/arm/meson.build | 1 +
include/hw/arm/aspeed_soc.h | 26 +-
3 files changed, 579 insertions(+), 2 deletions(-)
create mode 100644 hw/arm/aspeed_ast27x0.c
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
new file mode 100644
index 00..754c963230
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0.c
@@ -0,0 +1,554 @@
+/*
+ * ASPEED SoC 27x0 family
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Implementation extracted from the AST2600 and adapted for AST27x0.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "hw/i2c/aspeed_i2c.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/arm_gicv3.h"
+#include "qapi/qmp/qlist.h"
+
+static const hwaddr aspeed_soc_ast2700_memmap[] = {
+[ASPEED_DEV_SPI_BOOT] = 0x4,
+[ASPEED_DEV_SRAM] = 0x1000,
+[ASPEED_DEV_SDMC] = 0x12C0,
+[ASPEED_DEV_SCU] = 0x12C02000,
+[ASPEED_DEV_SCUIO] = 0x14C02000,
+[ASPEED_DEV_UART0] = 0X14C33000,
+[ASPEED_DEV_UART1] = 0X14C33100,
+[ASPEED_DEV_UART2] = 0X14C33200,
+[ASPEED_DEV_UART3] = 0X14C33300,
+[ASPEED_DEV_UART4] = 0X12C1A000,
+[ASPEED_DEV_UART5] = 0X14C33400,
+[ASPEED_DEV_UART6] = 0X14C33500,
+[ASPEED_DEV_UART7] = 0X14C33600,
+[ASPEED_DEV_UART8] = 0X14C33700,
+[ASPEED_DEV_UART9] = 0X14C33800,
+[ASPEED_DEV_UART10]= 0X14C33900,
+[ASPEED_DEV_UART11]= 0X14C33A00,
+[ASPEED_DEV_UART12]= 0X14C33B00,
+[ASPEED_DEV_WDT] = 0x14C37000,
+[ASPEED_DEV_VUART] = 0X14C3,
+[ASPEED_DEV_FMC] = 0x1400,
+[ASPEED_DEV_SPI0] = 0x1401,
+[ASPEED_DEV_SPI1] = 0x1402,
+[ASPEED_DEV_SPI2] = 0x1403,
+[ASPEED_DEV_SDRAM] = 0x4,
+[ASPEED_DEV_MII1] = 0x1404,
+[ASPEED_DEV_MII2] = 0x14040008,
+[ASPEED_DEV_MII3] = 0x14040010,
+[ASPEED_DEV_ETH1] = 0x1405,
+[ASPEED_DEV_ETH2] = 0x1406,
+[ASPEED_DEV_ETH3] = 0x1407,
+[ASPEED_DEV_EMMC] = 0x1209,
+[ASPEED_DEV_INTC] = 0x1210,
+[ASPEED_DEV_SLI] = 0x12C17000,
+[ASPEED_DEV_SLIIO] = 0x14C1E000,
+[ASPEED_GIC_DIST] = 0x1220,
+[ASPEED_GIC_REDIST]= 0x1228,
+};
+
+#define AST2700_MAX_IRQ 288
+
+/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
+static const int aspeed_soc_ast2700_irqmap[] = {
+[ASPEED_DEV_UART0] = 132,
+[ASPEED_DEV_UART1] = 132,
+[ASPEED_DEV_UART2] = 132,
+[ASPEED_DEV_UART3] = 132,
+[ASPEED_DEV_UART4] = 8,
+[ASPEED_DEV_UART5] = 132,
+[ASPEED_DEV_UART6] = 132,
+[ASPEED_DEV_UART7] = 132,
+[ASPEED_DEV_UART8] = 132,
+[ASPEED_DEV_UART9] = 132,
+[ASPEED_DEV_UART10]= 132,
+[ASPEED_DEV_UART11]= 132,
+[ASPEED_DEV_UART12]= 132,
+[ASPEED_DEV_FMC] = 131,
+[ASPEED_DEV_SDMC] = 0,
+[ASPEED_DEV_SCU] = 12,
+[ASPEED_DEV_ADC] = 130,
+[ASPEED_DEV_XDMA] = 5,
+[ASPEED_DEV_EMMC] = 15,
+[ASPEED_DEV_GPIO] = 11,
+[ASPEED_DEV_GPIO_1_8V] = 130,
+[ASPEED_DEV_RTC] = 13,
+[ASPEED_DEV_TIMER1]= 16,
+[ASPEED_DEV_TIMER2]= 17,
+[ASPEED_DEV_TIMER3]= 18,
+[ASPEED_DEV_TIMER4]= 19,
+[ASPEED_DEV_TIMER5]= 20,
+
RE: [PATCH v3 12/16] aspeed/soc: Add AST2700 support
Hi Cedric,
> On 4/16/24 11:18, Jamin Lin wrote:
> > Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35
> CPU).
> >
> > AST2700 SOC and its interrupt controller are too complex to handle in
> > the common Aspeed SoC framework. We introduce a new ast2700 class with
> > instance_init and realize handlers.
> >
> > AST2700 is a 64 bits quad core cpus and support 8 watchdog.
> > Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
> > In addition, update AspeedSocState to support scuio, sli, sliio and intc.
> >
> > Add TYPE_ASPEED27X0_SOC machine type.
> >
> > The SDMC controller is unlocked at SPL stage.
> > At present, only supports to emulate booting start from u-boot stage.
> > Set SDMC controller unlocked by default.
> >
> > In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
> > It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136.
> > And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is
> > connected to GICINT or-gates instead of GIC device.
> >
> > Signed-off-by: Troy Lee
> > Signed-off-by: Jamin Lin
>
> Before I forget, please see a little comment below regarding user creatable
> devices.
>
> The model looks fine. The interrupt controller part is more complex than the
> previous SoCs so I will come back to it later when I have more time.
Thanks for your kindly support.
> > ---
> > hw/arm/aspeed_ast27x0.c | 554
>
> > hw/arm/meson.build | 1 +
> > include/hw/arm/aspeed_soc.h | 26 +-
> > 3 files changed, 579 insertions(+), 2 deletions(-)
> > create mode 100644 hw/arm/aspeed_ast27x0.c
> >
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c new
> > file mode 100644 index 00..754c963230
> > --- /dev/null
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -0,0 +1,554 @@
> > +/*
> > + * ASPEED SoC 27x0 family
> > + *
> > + * Copyright (C) 2024 ASPEED Technology Inc.
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + *
> > + * Implementation extracted from the AST2600 and adapted for AST27x0.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qapi/error.h"
> > +#include "hw/misc/unimp.h"
> > +#include "hw/arm/aspeed_soc.h"
> > +#include "qemu/module.h"
> > +#include "qemu/error-report.h"
> > +#include "hw/i2c/aspeed_i2c.h"
> > +#include "net/net.h"
> > +#include "sysemu/sysemu.h"
> > +#include "hw/intc/arm_gicv3.h"
> > +#include "qapi/qmp/qlist.h"
> > +
> > +static const hwaddr aspeed_soc_ast2700_memmap[] = {
> > +[ASPEED_DEV_SPI_BOOT] = 0x4,
> > +[ASPEED_DEV_SRAM] = 0x1000,
> > +[ASPEED_DEV_SDMC] = 0x12C0,
> > +[ASPEED_DEV_SCU] = 0x12C02000,
> > +[ASPEED_DEV_SCUIO] = 0x14C02000,
> > +[ASPEED_DEV_UART0] = 0X14C33000,
> > +[ASPEED_DEV_UART1] = 0X14C33100,
> > +[ASPEED_DEV_UART2] = 0X14C33200,
> > +[ASPEED_DEV_UART3] = 0X14C33300,
> > +[ASPEED_DEV_UART4] = 0X12C1A000,
> > +[ASPEED_DEV_UART5] = 0X14C33400,
> > +[ASPEED_DEV_UART6] = 0X14C33500,
> > +[ASPEED_DEV_UART7] = 0X14C33600,
> > +[ASPEED_DEV_UART8] = 0X14C33700,
> > +[ASPEED_DEV_UART9] = 0X14C33800,
> > +[ASPEED_DEV_UART10]= 0X14C33900,
> > +[ASPEED_DEV_UART11]= 0X14C33A00,
> > +[ASPEED_DEV_UART12]= 0X14C33B00,
> > +[ASPEED_DEV_WDT] = 0x14C37000,
> > +[ASPEED_DEV_VUART] = 0X14C3,
> > +[ASPEED_DEV_FMC] = 0x1400,
> > +[ASPEED_DEV_SPI0] = 0x1401,
> > +[ASPEED_DEV_SPI1] = 0x1402,
> > +[ASPEED_DEV_SPI2] = 0x1403,
> > +[ASPEED_DEV_SDRAM] = 0x4,
> > +[ASPEED_DEV_MII1] = 0x1404,
> > +[ASPEED_DEV_MII2] = 0x14040008,
> > +[ASPEED_DEV_MII3] = 0x14040010,
> > +[ASPEED_DEV_ETH1] = 0x1405,
> > +[ASPEED_DEV_ETH2] = 0x1406,
> > +[ASPEED_DEV_ETH3] = 0x1407,
> > +[ASPEED_DEV_EMMC] = 0x1209,
> > +[ASPEED_DEV_INTC] = 0x1210,
> > +[ASPEED_DEV_SLI] = 0x12C17000,
> > +[ASPEED_DEV_SLIIO] = 0x14C1E000,
> > +[ASPEED_GIC_DIST] = 0x1220,
> > +[ASPEED_GIC_REDIST]= 0x1228,
> > +};
> > +
> > +#define AST2700_MAX_IRQ 288
> > +
> > +/* Shared Peripheral Interrupt values below are offset by -32 from
> > +datasheet */ static const int aspeed_soc_ast2700_irqmap[] = {
> > +[ASPEED_DEV_UART0] = 132,
> > +[ASPEED_DEV_UART1] = 132,
> > +[ASPEED_DEV_UART2] = 132,
> > +[ASPEED_DEV_UART3] = 132,
> > +[ASPEED_DEV_UART4] = 8,
> > +[ASPEED_DEV_UART5] = 132,
> > +[ASPEED_DEV_UART6] = 132,
> > +[ASPEED_DEV_UART7] = 132,
> > +[ASPEED_DEV_UART8] = 132,
> > +[ASPEED_DEV_UART9] = 132,
> > +[ASPEED_DEV_UART10]= 132,
> > +[ASPEED_DEV_UART11]= 132,
Re: [PATCH v3 12/16] aspeed/soc: Add AST2700 support
On 4/16/24 11:18, Jamin Lin wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
AST2700 is a 64 bits quad core cpus and support 8 watchdog.
Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
In addition, update AspeedSocState to support scuio, sli, sliio and intc.
Add TYPE_ASPEED27X0_SOC machine type.
The SDMC controller is unlocked at SPL stage.
At present, only supports to emulate booting
start from u-boot stage. Set SDMC controller
unlocked by default.
In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136.
And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is connected to
GICINT or-gates instead of GIC device.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Before I forget, please see a little comment below regarding user creatable
devices.
The model looks fine. The interrupt controller part is more complex than
the previous SoCs so I will come back to it later when I have more time.
---
hw/arm/aspeed_ast27x0.c | 554
hw/arm/meson.build | 1 +
include/hw/arm/aspeed_soc.h | 26 +-
3 files changed, 579 insertions(+), 2 deletions(-)
create mode 100644 hw/arm/aspeed_ast27x0.c
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
new file mode 100644
index 00..754c963230
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0.c
@@ -0,0 +1,554 @@
+/*
+ * ASPEED SoC 27x0 family
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Implementation extracted from the AST2600 and adapted for AST27x0.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "hw/i2c/aspeed_i2c.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/arm_gicv3.h"
+#include "qapi/qmp/qlist.h"
+
+static const hwaddr aspeed_soc_ast2700_memmap[] = {
+[ASPEED_DEV_SPI_BOOT] = 0x4,
+[ASPEED_DEV_SRAM] = 0x1000,
+[ASPEED_DEV_SDMC] = 0x12C0,
+[ASPEED_DEV_SCU] = 0x12C02000,
+[ASPEED_DEV_SCUIO] = 0x14C02000,
+[ASPEED_DEV_UART0] = 0X14C33000,
+[ASPEED_DEV_UART1] = 0X14C33100,
+[ASPEED_DEV_UART2] = 0X14C33200,
+[ASPEED_DEV_UART3] = 0X14C33300,
+[ASPEED_DEV_UART4] = 0X12C1A000,
+[ASPEED_DEV_UART5] = 0X14C33400,
+[ASPEED_DEV_UART6] = 0X14C33500,
+[ASPEED_DEV_UART7] = 0X14C33600,
+[ASPEED_DEV_UART8] = 0X14C33700,
+[ASPEED_DEV_UART9] = 0X14C33800,
+[ASPEED_DEV_UART10]= 0X14C33900,
+[ASPEED_DEV_UART11]= 0X14C33A00,
+[ASPEED_DEV_UART12]= 0X14C33B00,
+[ASPEED_DEV_WDT] = 0x14C37000,
+[ASPEED_DEV_VUART] = 0X14C3,
+[ASPEED_DEV_FMC] = 0x1400,
+[ASPEED_DEV_SPI0] = 0x1401,
+[ASPEED_DEV_SPI1] = 0x1402,
+[ASPEED_DEV_SPI2] = 0x1403,
+[ASPEED_DEV_SDRAM] = 0x4,
+[ASPEED_DEV_MII1] = 0x1404,
+[ASPEED_DEV_MII2] = 0x14040008,
+[ASPEED_DEV_MII3] = 0x14040010,
+[ASPEED_DEV_ETH1] = 0x1405,
+[ASPEED_DEV_ETH2] = 0x1406,
+[ASPEED_DEV_ETH3] = 0x1407,
+[ASPEED_DEV_EMMC] = 0x1209,
+[ASPEED_DEV_INTC] = 0x1210,
+[ASPEED_DEV_SLI] = 0x12C17000,
+[ASPEED_DEV_SLIIO] = 0x14C1E000,
+[ASPEED_GIC_DIST] = 0x1220,
+[ASPEED_GIC_REDIST]= 0x1228,
+};
+
+#define AST2700_MAX_IRQ 288
+
+/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
+static const int aspeed_soc_ast2700_irqmap[] = {
+[ASPEED_DEV_UART0] = 132,
+[ASPEED_DEV_UART1] = 132,
+[ASPEED_DEV_UART2] = 132,
+[ASPEED_DEV_UART3] = 132,
+[ASPEED_DEV_UART4] = 8,
+[ASPEED_DEV_UART5] = 132,
+[ASPEED_DEV_UART6] = 132,
+[ASPEED_DEV_UART7] = 132,
+[ASPEED_DEV_UART8] = 132,
+[ASPEED_DEV_UART9] = 132,
+[ASPEED_DEV_UART10]= 132,
+[ASPEED_DEV_UART11]= 132,
+[ASPEED_DEV_UART12]= 132,
+[ASPEED_DEV_FMC] = 131,
+[ASPEED_DEV_SDMC] = 0,
+[ASPEED_DEV_SCU] = 12,
+[ASPEED_DEV_ADC] = 130,
+[ASPEED_DEV_XDMA] = 5,
+[ASPEED_DEV_EMMC] = 15,
+[ASPEED_DEV_GPIO] = 11,
+[ASPEED_DEV_GPIO_1_8V] = 130,
+[ASPEED_DEV_RTC] = 13,
+[ASPEED_DEV_TIMER1]= 16,
+[ASPEED_DEV_TIMER2]= 17,
+[ASPEED_DEV_TIMER3]= 18,
+[ASPEED_DEV_TIMER4]= 19,
+[ASPEED_DEV_TIMER5]=
[PATCH v3 12/16] aspeed/soc: Add AST2700 support
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
AST2700 is a 64 bits quad core cpus and support 8 watchdog.
Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
In addition, update AspeedSocState to support scuio, sli, sliio and intc.
Add TYPE_ASPEED27X0_SOC machine type.
The SDMC controller is unlocked at SPL stage.
At present, only supports to emulate booting
start from u-boot stage. Set SDMC controller
unlocked by default.
In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136.
And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is connected to
GICINT or-gates instead of GIC device.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 554
hw/arm/meson.build | 1 +
include/hw/arm/aspeed_soc.h | 26 +-
3 files changed, 579 insertions(+), 2 deletions(-)
create mode 100644 hw/arm/aspeed_ast27x0.c
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
new file mode 100644
index 00..754c963230
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0.c
@@ -0,0 +1,554 @@
+/*
+ * ASPEED SoC 27x0 family
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Implementation extracted from the AST2600 and adapted for AST27x0.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "hw/i2c/aspeed_i2c.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/arm_gicv3.h"
+#include "qapi/qmp/qlist.h"
+
+static const hwaddr aspeed_soc_ast2700_memmap[] = {
+[ASPEED_DEV_SPI_BOOT] = 0x4,
+[ASPEED_DEV_SRAM] = 0x1000,
+[ASPEED_DEV_SDMC] = 0x12C0,
+[ASPEED_DEV_SCU] = 0x12C02000,
+[ASPEED_DEV_SCUIO] = 0x14C02000,
+[ASPEED_DEV_UART0] = 0X14C33000,
+[ASPEED_DEV_UART1] = 0X14C33100,
+[ASPEED_DEV_UART2] = 0X14C33200,
+[ASPEED_DEV_UART3] = 0X14C33300,
+[ASPEED_DEV_UART4] = 0X12C1A000,
+[ASPEED_DEV_UART5] = 0X14C33400,
+[ASPEED_DEV_UART6] = 0X14C33500,
+[ASPEED_DEV_UART7] = 0X14C33600,
+[ASPEED_DEV_UART8] = 0X14C33700,
+[ASPEED_DEV_UART9] = 0X14C33800,
+[ASPEED_DEV_UART10]= 0X14C33900,
+[ASPEED_DEV_UART11]= 0X14C33A00,
+[ASPEED_DEV_UART12]= 0X14C33B00,
+[ASPEED_DEV_WDT] = 0x14C37000,
+[ASPEED_DEV_VUART] = 0X14C3,
+[ASPEED_DEV_FMC] = 0x1400,
+[ASPEED_DEV_SPI0] = 0x1401,
+[ASPEED_DEV_SPI1] = 0x1402,
+[ASPEED_DEV_SPI2] = 0x1403,
+[ASPEED_DEV_SDRAM] = 0x4,
+[ASPEED_DEV_MII1] = 0x1404,
+[ASPEED_DEV_MII2] = 0x14040008,
+[ASPEED_DEV_MII3] = 0x14040010,
+[ASPEED_DEV_ETH1] = 0x1405,
+[ASPEED_DEV_ETH2] = 0x1406,
+[ASPEED_DEV_ETH3] = 0x1407,
+[ASPEED_DEV_EMMC] = 0x1209,
+[ASPEED_DEV_INTC] = 0x1210,
+[ASPEED_DEV_SLI] = 0x12C17000,
+[ASPEED_DEV_SLIIO] = 0x14C1E000,
+[ASPEED_GIC_DIST] = 0x1220,
+[ASPEED_GIC_REDIST]= 0x1228,
+};
+
+#define AST2700_MAX_IRQ 288
+
+/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
+static const int aspeed_soc_ast2700_irqmap[] = {
+[ASPEED_DEV_UART0] = 132,
+[ASPEED_DEV_UART1] = 132,
+[ASPEED_DEV_UART2] = 132,
+[ASPEED_DEV_UART3] = 132,
+[ASPEED_DEV_UART4] = 8,
+[ASPEED_DEV_UART5] = 132,
+[ASPEED_DEV_UART6] = 132,
+[ASPEED_DEV_UART7] = 132,
+[ASPEED_DEV_UART8] = 132,
+[ASPEED_DEV_UART9] = 132,
+[ASPEED_DEV_UART10]= 132,
+[ASPEED_DEV_UART11]= 132,
+[ASPEED_DEV_UART12]= 132,
+[ASPEED_DEV_FMC] = 131,
+[ASPEED_DEV_SDMC] = 0,
+[ASPEED_DEV_SCU] = 12,
+[ASPEED_DEV_ADC] = 130,
+[ASPEED_DEV_XDMA] = 5,
+[ASPEED_DEV_EMMC] = 15,
+[ASPEED_DEV_GPIO] = 11,
+[ASPEED_DEV_GPIO_1_8V] = 130,
+[ASPEED_DEV_RTC] = 13,
+[ASPEED_DEV_TIMER1]= 16,
+[ASPEED_DEV_TIMER2]= 17,
+[ASPEED_DEV_TIMER3]= 18,
+[ASPEED_DEV_TIMER4]= 19,
+[ASPEED_DEV_TIMER5]= 20,
+[ASPEED_DEV_TIMER6]= 21,
+[ASPEED_DEV_TIMER7]= 22,
+[ASPEED_DEV_TIMER8]= 23,
+[ASPEED_DEV_WDT] = 131,
+[ASPEED_DEV_PWM] = 131,
+[ASPEED_DEV_LPC] = 128,
+[ASPEED_DEV_IBT] = 128,
+[ASPEED_DEV_I2C] =
