Re: [PATCH v3 2/2] sifive_u: Connect the SiFive PWM device
On Thu, Sep 9, 2021 at 2:37 PM Bin Meng wrote:
>
> On Thu, Sep 9, 2021 at 11:55 AM Alistair Francis
> wrote:
> >
> > From: Alistair Francis
> >
> > Connect the SiFive PWM device and expose it via the device tree.
> >
> > Signed-off-by: Alistair Francis
> > ---
> > docs/system/riscv/sifive_u.rst | 1 +
> > include/hw/riscv/sifive_u.h| 14 -
> > hw/riscv/sifive_u.c| 55 +-
> > hw/timer/sifive_pwm.c | 1 +
> > hw/riscv/Kconfig | 1 +
> > 5 files changed, 70 insertions(+), 2 deletions(-)
> >
> > diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
> > index 01108b5ecc..7c65e9c440 100644
> > --- a/docs/system/riscv/sifive_u.rst
> > +++ b/docs/system/riscv/sifive_u.rst
> > @@ -24,6 +24,7 @@ The ``sifive_u`` machine supports the following devices:
> > * 2 QSPI controllers
> > * 1 ISSI 25WP256 flash
> > * 1 SD card in SPI mode
> > +* PWM0 and PWM1
> >
> > Please note the real world HiFive Unleashed board has a fixed
> > configuration of
> > 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit
> > mode.
> > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> > index 2656b39808..f71c90c94c 100644
> > --- a/include/hw/riscv/sifive_u.h
> > +++ b/include/hw/riscv/sifive_u.h
> > @@ -27,6 +27,7 @@
> > #include "hw/misc/sifive_u_otp.h"
> > #include "hw/misc/sifive_u_prci.h"
> > #include "hw/ssi/sifive_spi.h"
> > +#include "hw/timer/sifive_pwm.h"
> >
> > #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
> > #define RISCV_U_SOC(obj) \
> > @@ -49,6 +50,7 @@ typedef struct SiFiveUSoCState {
> > SiFiveSPIState spi0;
> > SiFiveSPIState spi2;
> > CadenceGEMState gem;
> > +SiFivePwmState pwm[2];
> >
> > uint32_t serial;
> > char *cpu_type;
> > @@ -92,7 +94,9 @@ enum {
> > SIFIVE_U_DEV_FLASH0,
> > SIFIVE_U_DEV_DRAM,
> > SIFIVE_U_DEV_GEM,
> > -SIFIVE_U_DEV_GEM_MGMT
> > +SIFIVE_U_DEV_GEM_MGMT,
> > +SIFIVE_U_DEV_PWM0,
> > +SIFIVE_U_DEV_PWM1
> > };
> >
> > enum {
> > @@ -126,6 +130,14 @@ enum {
> > SIFIVE_U_PDMA_IRQ5 = 28,
> > SIFIVE_U_PDMA_IRQ6 = 29,
> > SIFIVE_U_PDMA_IRQ7 = 30,
> > +SIFIVE_U_PWM0_IRQ0 = 42,
> > +SIFIVE_U_PWM0_IRQ1 = 43,
> > +SIFIVE_U_PWM0_IRQ2 = 44,
> > +SIFIVE_U_PWM0_IRQ3 = 45,
> > +SIFIVE_U_PWM1_IRQ0 = 46,
> > +SIFIVE_U_PWM1_IRQ1 = 47,
> > +SIFIVE_U_PWM1_IRQ2 = 48,
> > +SIFIVE_U_PWM1_IRQ3 = 49,
> > SIFIVE_U_QSPI0_IRQ = 51,
> > SIFIVE_U_GEM_IRQ = 53
> > };
> > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> > index 6cc1a62b0f..2301f5dd4f 100644
> > --- a/hw/riscv/sifive_u.c
> > +++ b/hw/riscv/sifive_u.c
> > @@ -17,6 +17,7 @@
> > * 7) DMA (Direct Memory Access Controller)
> > * 8) SPI0 connected to an SPI flash
> > * 9) SPI2 connected to an SD card
> > + * 10) PWM0 and PWM1
> > *
> > * This board currently generates devicetree dynamically that indicates at
> > least
> > * two harts and up to five harts.
> > @@ -75,6 +76,8 @@ static const MemMapEntry sifive_u_memmap[] = {
> > [SIFIVE_U_DEV_PRCI] = { 0x1000, 0x1000 },
> > [SIFIVE_U_DEV_UART0] ={ 0x1001, 0x1000 },
> > [SIFIVE_U_DEV_UART1] ={ 0x10011000, 0x1000 },
> > +[SIFIVE_U_DEV_PWM0] = { 0x1002, 0x1000 },
> > +[SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 },
> > [SIFIVE_U_DEV_QSPI0] ={ 0x1004, 0x1000 },
> > [SIFIVE_U_DEV_QSPI2] ={ 0x1005, 0x1000 },
> > [SIFIVE_U_DEV_GPIO] = { 0x1006, 0x1000 },
> > @@ -441,6 +444,38 @@ static void create_fdt(SiFiveUState *s, const
> > MemMapEntry *memmap,
> > qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
> > g_free(nodename);
> >
> > +nodename = g_strdup_printf("/soc/pwm@%lx",
> > +(long)memmap[SIFIVE_U_DEV_PWM0].base);
> > +qemu_fdt_add_subnode(fdt, nodename);
> > +qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
> > +qemu_fdt_setprop_cells(fdt, nodename, "reg",
> > +0x0, memmap[SIFIVE_U_DEV_PWM0].base,
> > +0x0, memmap[SIFIVE_U_DEV_PWM0].size);
> > +qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> > +qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
> > + SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1,
> > + SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3);
> > +qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> > + prci_phandle, PRCI_CLK_TLCLK);
> > +qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
> > +g_free(nodename);
> > +
> > +nodename = g_strdup_printf("/soc/pwm@%lx",
> > +(long)memmap[SIFIVE_U_DEV_PWM1].base);
> > +qemu_fdt_add_subnode(fdt, nodename);
> > +qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
> > +qemu_fdt_setprop_cells(fdt, nodename, "reg",
> > +0x0, memmap
Re: [PATCH v3 2/2] sifive_u: Connect the SiFive PWM device
On Thu, Sep 9, 2021 at 11:55 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Connect the SiFive PWM device and expose it via the device tree.
>
> Signed-off-by: Alistair Francis
> ---
> docs/system/riscv/sifive_u.rst | 1 +
> include/hw/riscv/sifive_u.h| 14 -
> hw/riscv/sifive_u.c| 55 +-
> hw/timer/sifive_pwm.c | 1 +
> hw/riscv/Kconfig | 1 +
> 5 files changed, 70 insertions(+), 2 deletions(-)
>
> diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
> index 01108b5ecc..7c65e9c440 100644
> --- a/docs/system/riscv/sifive_u.rst
> +++ b/docs/system/riscv/sifive_u.rst
> @@ -24,6 +24,7 @@ The ``sifive_u`` machine supports the following devices:
> * 2 QSPI controllers
> * 1 ISSI 25WP256 flash
> * 1 SD card in SPI mode
> +* PWM0 and PWM1
>
> Please note the real world HiFive Unleashed board has a fixed configuration
> of
> 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit
> mode.
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 2656b39808..f71c90c94c 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -27,6 +27,7 @@
> #include "hw/misc/sifive_u_otp.h"
> #include "hw/misc/sifive_u_prci.h"
> #include "hw/ssi/sifive_spi.h"
> +#include "hw/timer/sifive_pwm.h"
>
> #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
> #define RISCV_U_SOC(obj) \
> @@ -49,6 +50,7 @@ typedef struct SiFiveUSoCState {
> SiFiveSPIState spi0;
> SiFiveSPIState spi2;
> CadenceGEMState gem;
> +SiFivePwmState pwm[2];
>
> uint32_t serial;
> char *cpu_type;
> @@ -92,7 +94,9 @@ enum {
> SIFIVE_U_DEV_FLASH0,
> SIFIVE_U_DEV_DRAM,
> SIFIVE_U_DEV_GEM,
> -SIFIVE_U_DEV_GEM_MGMT
> +SIFIVE_U_DEV_GEM_MGMT,
> +SIFIVE_U_DEV_PWM0,
> +SIFIVE_U_DEV_PWM1
> };
>
> enum {
> @@ -126,6 +130,14 @@ enum {
> SIFIVE_U_PDMA_IRQ5 = 28,
> SIFIVE_U_PDMA_IRQ6 = 29,
> SIFIVE_U_PDMA_IRQ7 = 30,
> +SIFIVE_U_PWM0_IRQ0 = 42,
> +SIFIVE_U_PWM0_IRQ1 = 43,
> +SIFIVE_U_PWM0_IRQ2 = 44,
> +SIFIVE_U_PWM0_IRQ3 = 45,
> +SIFIVE_U_PWM1_IRQ0 = 46,
> +SIFIVE_U_PWM1_IRQ1 = 47,
> +SIFIVE_U_PWM1_IRQ2 = 48,
> +SIFIVE_U_PWM1_IRQ3 = 49,
> SIFIVE_U_QSPI0_IRQ = 51,
> SIFIVE_U_GEM_IRQ = 53
> };
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 6cc1a62b0f..2301f5dd4f 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -17,6 +17,7 @@
> * 7) DMA (Direct Memory Access Controller)
> * 8) SPI0 connected to an SPI flash
> * 9) SPI2 connected to an SD card
> + * 10) PWM0 and PWM1
> *
> * This board currently generates devicetree dynamically that indicates at
> least
> * two harts and up to five harts.
> @@ -75,6 +76,8 @@ static const MemMapEntry sifive_u_memmap[] = {
> [SIFIVE_U_DEV_PRCI] = { 0x1000, 0x1000 },
> [SIFIVE_U_DEV_UART0] ={ 0x1001, 0x1000 },
> [SIFIVE_U_DEV_UART1] ={ 0x10011000, 0x1000 },
> +[SIFIVE_U_DEV_PWM0] = { 0x1002, 0x1000 },
> +[SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 },
> [SIFIVE_U_DEV_QSPI0] ={ 0x1004, 0x1000 },
> [SIFIVE_U_DEV_QSPI2] ={ 0x1005, 0x1000 },
> [SIFIVE_U_DEV_GPIO] = { 0x1006, 0x1000 },
> @@ -441,6 +444,38 @@ static void create_fdt(SiFiveUState *s, const
> MemMapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
> g_free(nodename);
>
> +nodename = g_strdup_printf("/soc/pwm@%lx",
> +(long)memmap[SIFIVE_U_DEV_PWM0].base);
> +qemu_fdt_add_subnode(fdt, nodename);
> +qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
> +qemu_fdt_setprop_cells(fdt, nodename, "reg",
> +0x0, memmap[SIFIVE_U_DEV_PWM0].base,
> +0x0, memmap[SIFIVE_U_DEV_PWM0].size);
> +qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> +qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
> + SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1,
> + SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3);
> +qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> + prci_phandle, PRCI_CLK_TLCLK);
> +qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
> +g_free(nodename);
> +
> +nodename = g_strdup_printf("/soc/pwm@%lx",
> +(long)memmap[SIFIVE_U_DEV_PWM1].base);
> +qemu_fdt_add_subnode(fdt, nodename);
> +qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
> +qemu_fdt_setprop_cells(fdt, nodename, "reg",
> +0x0, memmap[SIFIVE_U_DEV_PWM1].base,
> +0x0, memmap[SIFIVE_U_DEV_PWM1].size);
> +qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> +qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
> + SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1,
> +
[PATCH v3 2/2] sifive_u: Connect the SiFive PWM device
From: Alistair Francis
Connect the SiFive PWM device and expose it via the device tree.
Signed-off-by: Alistair Francis
---
docs/system/riscv/sifive_u.rst | 1 +
include/hw/riscv/sifive_u.h| 14 -
hw/riscv/sifive_u.c| 55 +-
hw/timer/sifive_pwm.c | 1 +
hw/riscv/Kconfig | 1 +
5 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
index 01108b5ecc..7c65e9c440 100644
--- a/docs/system/riscv/sifive_u.rst
+++ b/docs/system/riscv/sifive_u.rst
@@ -24,6 +24,7 @@ The ``sifive_u`` machine supports the following devices:
* 2 QSPI controllers
* 1 ISSI 25WP256 flash
* 1 SD card in SPI mode
+* PWM0 and PWM1
Please note the real world HiFive Unleashed board has a fixed configuration of
1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 2656b39808..f71c90c94c 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -27,6 +27,7 @@
#include "hw/misc/sifive_u_otp.h"
#include "hw/misc/sifive_u_prci.h"
#include "hw/ssi/sifive_spi.h"
+#include "hw/timer/sifive_pwm.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
#define RISCV_U_SOC(obj) \
@@ -49,6 +50,7 @@ typedef struct SiFiveUSoCState {
SiFiveSPIState spi0;
SiFiveSPIState spi2;
CadenceGEMState gem;
+SiFivePwmState pwm[2];
uint32_t serial;
char *cpu_type;
@@ -92,7 +94,9 @@ enum {
SIFIVE_U_DEV_FLASH0,
SIFIVE_U_DEV_DRAM,
SIFIVE_U_DEV_GEM,
-SIFIVE_U_DEV_GEM_MGMT
+SIFIVE_U_DEV_GEM_MGMT,
+SIFIVE_U_DEV_PWM0,
+SIFIVE_U_DEV_PWM1
};
enum {
@@ -126,6 +130,14 @@ enum {
SIFIVE_U_PDMA_IRQ5 = 28,
SIFIVE_U_PDMA_IRQ6 = 29,
SIFIVE_U_PDMA_IRQ7 = 30,
+SIFIVE_U_PWM0_IRQ0 = 42,
+SIFIVE_U_PWM0_IRQ1 = 43,
+SIFIVE_U_PWM0_IRQ2 = 44,
+SIFIVE_U_PWM0_IRQ3 = 45,
+SIFIVE_U_PWM1_IRQ0 = 46,
+SIFIVE_U_PWM1_IRQ1 = 47,
+SIFIVE_U_PWM1_IRQ2 = 48,
+SIFIVE_U_PWM1_IRQ3 = 49,
SIFIVE_U_QSPI0_IRQ = 51,
SIFIVE_U_GEM_IRQ = 53
};
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6cc1a62b0f..2301f5dd4f 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -17,6 +17,7 @@
* 7) DMA (Direct Memory Access Controller)
* 8) SPI0 connected to an SPI flash
* 9) SPI2 connected to an SD card
+ * 10) PWM0 and PWM1
*
* This board currently generates devicetree dynamically that indicates at
least
* two harts and up to five harts.
@@ -75,6 +76,8 @@ static const MemMapEntry sifive_u_memmap[] = {
[SIFIVE_U_DEV_PRCI] = { 0x1000, 0x1000 },
[SIFIVE_U_DEV_UART0] ={ 0x1001, 0x1000 },
[SIFIVE_U_DEV_UART1] ={ 0x10011000, 0x1000 },
+[SIFIVE_U_DEV_PWM0] = { 0x1002, 0x1000 },
+[SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 },
[SIFIVE_U_DEV_QSPI0] ={ 0x1004, 0x1000 },
[SIFIVE_U_DEV_QSPI2] ={ 0x1005, 0x1000 },
[SIFIVE_U_DEV_GPIO] = { 0x1006, 0x1000 },
@@ -441,6 +444,38 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
*memmap,
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
+nodename = g_strdup_printf("/soc/pwm@%lx",
+(long)memmap[SIFIVE_U_DEV_PWM0].base);
+qemu_fdt_add_subnode(fdt, nodename);
+qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
+qemu_fdt_setprop_cells(fdt, nodename, "reg",
+0x0, memmap[SIFIVE_U_DEV_PWM0].base,
+0x0, memmap[SIFIVE_U_DEV_PWM0].size);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
+ SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1,
+ SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3);
+qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
+qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
+g_free(nodename);
+
+nodename = g_strdup_printf("/soc/pwm@%lx",
+(long)memmap[SIFIVE_U_DEV_PWM1].base);
+qemu_fdt_add_subnode(fdt, nodename);
+qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
+qemu_fdt_setprop_cells(fdt, nodename, "reg",
+0x0, memmap[SIFIVE_U_DEV_PWM1].base,
+0x0, memmap[SIFIVE_U_DEV_PWM1].size);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
+ SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1,
+ SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3);
+qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
+qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
+g_free(nodename);
+
nodename = g_strdup_printf("/soc/serial@%lx",
