Re: [PATCH v3 2/7] target/riscv: Add a virtualised MMU Mode

[Alistair Francis]

On Tue, Nov 3, 2020 at 12:20 PM Richard Henderson
 wrote:
>
> On 11/3/20 11:50 AM, Alistair Francis wrote:
> > @@ -30,6 +30,10 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
> >  #ifdef CONFIG_USER_ONLY
> >  return 0;
> >  #else
> > +if (riscv_cpu_virt_enabled(env)) {
> > +return env->priv | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
> > +}
>
> Still setting this bit here, incorrectly.

Argh! I must have dreamed fixing it. Sending a new version now.

Alistair

>
>
> r~

Re: [PATCH v3 2/7] target/riscv: Add a virtualised MMU Mode

[Richard Henderson]

On 11/3/20 11:50 AM, Alistair Francis wrote:
> @@ -30,6 +30,10 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
>  #ifdef CONFIG_USER_ONLY
>  return 0;
>  #else
> +if (riscv_cpu_virt_enabled(env)) {
> +return env->priv | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
> +}

Still setting this bit here, incorrectly.


r~

[PATCH v3 2/7] target/riscv: Add a virtualised MMU Mode

[Alistair Francis]

Add a new MMU mode that includes the current virt mode.

Signed-off-by: Alistair Francis 
---
 target/riscv/cpu-param.h  | 10 +-
 target/riscv/cpu.h|  4 +++-
 target/riscv/cpu_helper.c |  6 +-
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index 664fc1d371..0db6e23140 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -18,6 +18,14 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
 #endif
 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
-#define NB_MMU_MODES 4
+/*
+ * The current MMU Modes are:
+ *  - U  mode 0b000
+ *  - S  mode 0b001
+ *  - M  mode 0b011
+ *  - HU mode 0b100
+ *  - HS mode 0b101
+ */
+#define NB_MMU_MODES 6
 
 #endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 87b68affa8..5d8e54c426 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -363,7 +363,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 
-#define TB_FLAGS_MMU_MASK   3
+#define TB_FLAGS_MMU_MASK   7
+#define TB_FLAGS_PRIV_MMU_MASK3
+#define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 
 typedef CPURISCVState CPUArchState;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 3eb3a034db..453e4c6d8a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -30,6 +30,10 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 #ifdef CONFIG_USER_ONLY
 return 0;
 #else
+if (riscv_cpu_virt_enabled(env)) {
+return env->priv | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
+}
+
 return env->priv;
 #endif
 }
@@ -323,7 +327,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr 
*physical,
  * (riscv_cpu_do_interrupt) is correct */
 MemTxResult res;
 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
-int mode = mmu_idx;
+int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
 bool use_background = false;
 
 /*
-- 
2.28.0