Re: [PATCH v4 11/16] aspeed/intc: Add AST2700 support
+static void aspeed_2700_intc_class_init(ObjectClass *klass, void
+*data) {
+DeviceClass *dc = DEVICE_CLASS(klass);
+AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+dc->desc = "ASPEED 2700 INTC Controller";
+aic->num_lines = 32;
+aic->num_ints = 9;
Use ASPEED_INTC_NR_INTS ?
I am considering to support INTC model for future BMC SOCs.
For example, if the num_ints has been changed to "18" in the future BMC Socs,
users only need to update ASPEED_INTC_NR_INTS and
Create a aspeed__intc_class_init to set its "aic->num_ints 18".
That was why I set aic->num_ints 9 in aspeed_2700_intc_class_init.
OK. This is minor.
Thanks,
C.
RE: [PATCH v4 11/16] aspeed/intc: Add AST2700 support
Hi Cedric, > From: Cédric Le Goater > Subject: Re: [PATCH v4 11/16] aspeed/intc: Add AST2700 support > > On 5/27/24 10:02, Jamin Lin wrote: > > AST2700 interrupt controller(INTC) provides hardware interrupt > > interfaces to interrupt of processors PSP, SSP and TSP. In INTC, each > > interrupt of INT 128 to INT136 combines 32 interrupts. > > > > Introduce a new aspeed_intc class with instance_init and realize handlers. > > > > So far, this model only supports GICINT128 to GICINT136. > > It creates 9 GICINT or-gates to connect 32 interrupts sources from > > GICINT128 to GICINT136 as IRQ GPIO-OUTPUT pins. > > Then, this model registers IRQ handler with its IRQ GPIO-INPUT pins > > which connect to GICINT or-gates. And creates 9 GICINT IRQ GPIO-OUTPUT > > pins which connect to GIC device with GIC IRQ 128 to 136. > > > > If one interrupt source from GICINT128 to GICINT136 set irq, the > > OR-GATE irq callback function is called and set irq to INTC by OR-GATE > > GPIO-OUTPUT pins. Then, the INTC irq callback function is called and > > set irq to GIC by its GICINT IRQ GPIO-OUTPUT pins. Finally, the GIC > > irq callback function is called and set irq to CPUs and CPUs execute > > Interrupt Service Routine (ISR). > > > > Block diagram of GICINT132: > > > > GICINT132 > >ETH1+---+ > > +>+0 3| > >ETH2| 4| > > +>+1 5| > >ETH3| 6| > > +>+219| INTC > GIC > >UART0 | 20|+--+ > > +>+721|| | > +--+ > >UART1 | 22||orgate0 +> > output_pin0+--->+GIC128| > > +>+823|| | > | | > >UART2 | 24||orgate1 +> > output_pin1+--->+GIC129| > > +>+925|| | > | | > >UART3 | 26||orgate2 +> > output_pin2+--->+GIC130| > > +->10 27|| | > | | > >UART5 | 28||orgate3 +> > output_pin3+--->+GIC131| > > +>+11 29|| | > | | > >UART6 | +--->+orgate4 +> > output_pin4+--->+GIC132| > > +>+12 30|| | > | | > >UART7 | 31||orgate5 +> > output_pin5+--->+GIC133| > > +>+13 || | > | | > >UART8 | OR[0:31] ||orgate6 +> > output_pin6+--->+GIC134| > > -->14 || | > | | > >UART9 | ||orgate7 +> > output_pin7+--->+GIC135| > > ->+15 || | > | | > >UART10 | ||orgate8 +> > output_pin8+--->+GIC136| > > ->+16 || | > +--+ > >UART11 | |+--+ > > +>+17 | > >UART12 | | > > +->18 | > >| | > >| | > >| | > >+---+ > > > > Signed-off-by: Troy Lee > > Signed-off-by: Jamin Lin > > --- > > hw/intc/aspeed_intc.c | 355 > ++ > > hw/intc/meson.build | 1 + > > hw/intc/trace-events | 6 + > > include/hw/intc/aspeed_intc.h | 46 + > > 4 files changed, 408 insertions(+) > > create mode 100644 hw/intc/aspeed_intc.c > > create mode 100644 include/hw/intc/aspeed_intc.h > > > > diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c new file > > mode 100644 index 00..cb6111d79c > > --- /dev/null > > +++ b/hw/intc/aspeed_intc.c > > @@ -0,0 +1,355 @@ > > +/* > > + * ASPEED INTC Controller > > + * > > + * Copyright (C) 2024 ASPEED Technology Inc. > > + * >
Re: [PATCH v4 11/16] aspeed/intc: Add AST2700 support
On 5/27/24 10:02, Jamin Lin wrote: AST2700 interrupt controller(INTC) provides hardware interrupt interfaces to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of INT 128 to INT136 combines 32 interrupts. Introduce a new aspeed_intc class with instance_init and realize handlers. So far, this model only supports GICINT128 to GICINT136. It creates 9 GICINT or-gates to connect 32 interrupts sources from GICINT128 to GICINT136 as IRQ GPIO-OUTPUT pins. Then, this model registers IRQ handler with its IRQ GPIO-INPUT pins which connect to GICINT or-gates. And creates 9 GICINT IRQ GPIO-OUTPUT pins which connect to GIC device with GIC IRQ 128 to 136. If one interrupt source from GICINT128 to GICINT136 set irq, the OR-GATE irq callback function is called and set irq to INTC by OR-GATE GPIO-OUTPUT pins. Then, the INTC irq callback function is called and set irq to GIC by its GICINT IRQ GPIO-OUTPUT pins. Finally, the GIC irq callback function is called and set irq to CPUs and CPUs execute Interrupt Service Routine (ISR). Block diagram of GICINT132: GICINT132 ETH1+---+ +>+0 3| ETH2| 4| +>+1 5| ETH3| 6| +>+219| INTC GIC UART0 | 20|+--+ +>+721|| | +--+ UART1 | 22||orgate0 +> output_pin0+--->+GIC128| +>+823|| || | UART2 | 24||orgate1 +> output_pin1+--->+GIC129| +>+925|| || | UART3 | 26||orgate2 +> output_pin2+--->+GIC130| +->10 27|| || | UART5 | 28||orgate3 +> output_pin3+--->+GIC131| +>+11 29|| || | UART6 | +--->+orgate4 +> output_pin4+--->+GIC132| +>+12 30|| || | UART7 | 31||orgate5 +> output_pin5+--->+GIC133| +>+13 || || | UART8 | OR[0:31] ||orgate6 +> output_pin6+--->+GIC134| -->14 || || | UART9 | ||orgate7 +> output_pin7+--->+GIC135| ->+15 || || | UART10 | ||orgate8 +> output_pin8+--->+GIC136| ->+16 || | +--+ UART11 | |+--+ +>+17 | UART12 | | +->18 | | | | | | | +---+ Signed-off-by: Troy Lee Signed-off-by: Jamin Lin --- hw/intc/aspeed_intc.c | 355 ++ hw/intc/meson.build | 1 + hw/intc/trace-events | 6 + include/hw/intc/aspeed_intc.h | 46 + 4 files changed, 408 insertions(+) create mode 100644 hw/intc/aspeed_intc.c create mode 100644 include/hw/intc/aspeed_intc.h diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c new file mode 100644 index 00..cb6111d79c --- /dev/null +++ b/hw/intc/aspeed_intc.c @@ -0,0 +1,355 @@ +/* + * ASPEED INTC Controller + * + * Copyright (C) 2024 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/intc/aspeed_intc.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/intc/arm_gicv3.h" +#include "trace.h" +#include "hw/registerfields.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" + +/* INTC Registers */ +REG32(GICINT128_EN, 0x1000) +REG32(GICINT128_STATUS, 0x1004) +REG32(GICINT129_EN, 0x1100) +REG32(GICINT129_STATUS, 0x1104) +REG32(GICINT130_EN, 0x1200) +REG32(GICINT130_STATUS, 0x1204) +REG32(GICINT131_EN, 0x1300) +REG32(GICINT131_STATUS, 0x1304) +REG32(GICINT132_EN, 0x1400) +REG32(GICINT132_STATUS, 0x1404) +REG32(GICINT133_EN, 0x1500) +REG32(GICINT133_STATUS, 0x1504) +REG32(GICINT134_EN, 0x1600) +REG32(GICINT134_STATUS, 0x1604) +REG32(GICINT135_EN, 0x1700)
[PATCH v4 11/16] aspeed/intc: Add AST2700 support
AST2700 interrupt controller(INTC) provides hardware interrupt interfaces to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of INT 128 to INT136 combines 32 interrupts. Introduce a new aspeed_intc class with instance_init and realize handlers. So far, this model only supports GICINT128 to GICINT136. It creates 9 GICINT or-gates to connect 32 interrupts sources from GICINT128 to GICINT136 as IRQ GPIO-OUTPUT pins. Then, this model registers IRQ handler with its IRQ GPIO-INPUT pins which connect to GICINT or-gates. And creates 9 GICINT IRQ GPIO-OUTPUT pins which connect to GIC device with GIC IRQ 128 to 136. If one interrupt source from GICINT128 to GICINT136 set irq, the OR-GATE irq callback function is called and set irq to INTC by OR-GATE GPIO-OUTPUT pins. Then, the INTC irq callback function is called and set irq to GIC by its GICINT IRQ GPIO-OUTPUT pins. Finally, the GIC irq callback function is called and set irq to CPUs and CPUs execute Interrupt Service Routine (ISR). Block diagram of GICINT132: GICINT132 ETH1+---+ +>+0 3| ETH2| 4| +>+1 5| ETH3| 6| +>+219| INTC GIC UART0 | 20|+--+ +>+721|| | +--+ UART1 | 22||orgate0 +> output_pin0+--->+GIC128| +>+823|| || | UART2 | 24||orgate1 +> output_pin1+--->+GIC129| +>+925|| || | UART3 | 26||orgate2 +> output_pin2+--->+GIC130| +->10 27|| || | UART5 | 28||orgate3 +> output_pin3+--->+GIC131| +>+11 29|| || | UART6 | +--->+orgate4 +> output_pin4+--->+GIC132| +>+12 30|| || | UART7 | 31||orgate5 +> output_pin5+--->+GIC133| +>+13 || || | UART8 | OR[0:31] ||orgate6 +> output_pin6+--->+GIC134| -->14 || || | UART9 | ||orgate7 +> output_pin7+--->+GIC135| ->+15 || || | UART10 | ||orgate8 +> output_pin8+--->+GIC136| ->+16 || | +--+ UART11 | |+--+ +>+17 | UART12 | | +->18 | | | | | | | +---+ Signed-off-by: Troy Lee Signed-off-by: Jamin Lin --- hw/intc/aspeed_intc.c | 355 ++ hw/intc/meson.build | 1 + hw/intc/trace-events | 6 + include/hw/intc/aspeed_intc.h | 46 + 4 files changed, 408 insertions(+) create mode 100644 hw/intc/aspeed_intc.c create mode 100644 include/hw/intc/aspeed_intc.h diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c new file mode 100644 index 00..cb6111d79c --- /dev/null +++ b/hw/intc/aspeed_intc.c @@ -0,0 +1,355 @@ +/* + * ASPEED INTC Controller + * + * Copyright (C) 2024 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/intc/aspeed_intc.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/intc/arm_gicv3.h" +#include "trace.h" +#include "hw/registerfields.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" + +/* INTC Registers */ +REG32(GICINT128_EN, 0x1000) +REG32(GICINT128_STATUS, 0x1004) +REG32(GICINT129_EN, 0x1100) +REG32(GICINT129_STATUS, 0x1104) +REG32(GICINT130_EN, 0x1200) +REG32(GICINT130_STATUS, 0x1204) +REG32(GICINT131_EN, 0x1300) +REG32(GICINT131_STATUS, 0x1304) +REG32(GICINT132_EN, 0x1400) +REG32(GICINT132_STATUS, 0x1404) +REG32(GICINT133_EN, 0x1500) +REG32(GICINT133_STATUS, 0x1504) +REG32(GICINT134_EN, 0x1600) +REG32(GICINT134_STATUS, 0x1604) +REG32(GICINT135_EN, 0x1700) +REG32(GICINT135_STATUS, 0x1704) +REG32(GICINT136_EN, 0x1800)
