Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties

2022-01-18 Thread Weiwei Li 



在 2022/1/18 下午12:23, Alistair Francis 写道:

On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li  wrote:

Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
---
  target/riscv/cpu.c | 14 ++
  1 file changed, 14 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b487a8282c..628a782ba9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -694,9 +694,23 @@ static Property riscv_cpu_properties[] = {
  DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
  DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
  DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
+DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
+DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
  DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
+DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
+DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
+DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
+DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
+DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
+DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
+DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
+DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
+DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),

  /* These are experimental so mark with 'x-' */
+DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),

Looks like a rebase error

Alistair


Yeah. I'll fix this.

Regards,

Weiwei Li


  DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
  /* ePMP 0.9.3 */
  DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
--
2.17.1

Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties

2022-01-17 Thread Alistair Francis 
On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li  wrote:
>
> Signed-off-by: Weiwei Li 
> Signed-off-by: Junqiang Wang 
> ---
>  target/riscv/cpu.c | 14 ++
>  1 file changed, 14 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b487a8282c..628a782ba9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -694,9 +694,23 @@ static Property riscv_cpu_properties[] = {
>  DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
>  DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>  DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> +DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
> +DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
> +DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
>  DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> +DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
> +DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
> +DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
> +DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
> +DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
> +DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
> +DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
> +DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
> +DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
> +DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
>
>  /* These are experimental so mark with 'x-' */
> +DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),

Looks like a rebase error

Alistair

>  DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>  /* ePMP 0.9.3 */
>  DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> --
> 2.17.1
>
>

[PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties

2022-01-10 Thread Weiwei Li 
Signed-off-by: Weiwei Li 
Signed-off-by: Junqiang Wang 
---
 target/riscv/cpu.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b487a8282c..628a782ba9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -694,9 +694,23 @@ static Property riscv_cpu_properties[] = {
 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
+DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
+DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
+DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
+DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
+DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
+DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
+DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
+DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
+DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
+DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
+DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
 
 /* These are experimental so mark with 'x-' */
+DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
 /* ePMP 0.9.3 */
 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
-- 
2.17.1