On Wed, Apr 21, 2021 at 2:17 PM wrote:
>
> From: Kito Cheng
>
> Signed-off-by: Kito Cheng
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn32.decode | 4
> target/riscv/insn_trans/trans_rvb.c.inc | 18 ++
> 2 files changed, 22 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 0e321da37f4..d0b3f109b4e 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -598,3 +598,7 @@ vsetvl 100 . . 111 . 1010111 @r
> clz011000 00 . 001 . 0010011 @r2
> ctz011000 01 . 001 . 0010011 @r2
> cpop 011000 10 . 001 . 0010011 @r2
> +
> +andn 010 .. 111 . 0110011 @r
> +orn010 .. 110 . 0110011 @r
> +xnor 010 .. 100 . 0110011 @r
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index dbbd94e1015..73c4693a263 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -35,6 +35,24 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
> return gen_unary(ctx, a, tcg_gen_ctpop_tl);
> }
>
> +static bool trans_andn(DisasContext *ctx, arg_andn *a)
> +{
> +REQUIRE_EXT(ctx, RVB);
> +return gen_arith(ctx, a, tcg_gen_andc_tl);
> +}
> +
> +static bool trans_orn(DisasContext *ctx, arg_orn *a)
> +{
> +REQUIRE_EXT(ctx, RVB);
> +return gen_arith(ctx, a, tcg_gen_orc_tl);
> +}
> +
> +static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
> +{
> +REQUIRE_EXT(ctx, RVB);
> +return gen_arith(ctx, a, tcg_gen_eqv_tl);
> +}
> +
> /* RV64-only instructions */
> #ifdef TARGET_RISCV64
>
> --
> 2.17.1
>
>
