Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles
On 25/11/2021 12:47, Alistair Francis wrote:
On Wed, Nov 24, 2021 at 5:33 PM Philippe Mathieu-Daudé wrote:
Hi Frédéric,
On 11/24/21 07:55, Frédéric Pétrot wrote:
On 24/11/2021 07:12, Alistair Francis wrote:
On Sat, Nov 13, 2021 at 1:16 AM Frédéric Pétrot
wrote:
This patch is kind of a mess because several files have to be slightly
modified to allow for a new target. In the current status, we have done
our best to have RV64 and RV128 under the same RV64 umbrella, but there
is still work to do to have a single executable for both.
In particular, we have no atomic accesses for aligned 128-bit addresses.
Once this patch applied, adding risc128-sofmmu to --target-list produces
a (no so useful yet) executable.
I can't remember if we discussed this before, but do we need the
riscv128-sofmmu executable? Can we instead just use a riscv64-sofmmu
executable?
Hello Alistair,
Richard was also advocating for a single executable, but pointed out that
we need to disable mttcg because there is a need for specific tcg
support for
128-bit aligned atomics.
Given my understanding of that part of QEMU, I choose the easy way to
disable
it once and for all at compile time until we have that.
In rv128_base_cpu_init():
if (qemu_tcg_mttcg_enabled) {
/* Missing 128-bit aligned atomics */
error_report("128-bit RISC-V currently does not work"
" with Multi Threaded TCG. Please use:"
" -accel tcg,thread=single");
exit(EXIT_FAILURE);
}
That seems like a good option! I think we could add this to the CPU
realise function.
The problem with a riscv128-sofmmu executable is that it's hard to get
rid of in the future. We are very slowly moving towards a single
executable and adding a new one means we are stuck with it for a
while.
Alistair
Ooups, I replied yesterday to Philippe that I would work that out, but I
missed the reply all button, sorry.
Frédéric
Regards,
Phil.
--
+---+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.pet...@univ-grenoble-alpes.fr |
+---+
Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles
On Wed, Nov 24, 2021 at 5:33 PM Philippe Mathieu-Daudé wrote:
>
> Hi Frédéric,
>
> On 11/24/21 07:55, Frédéric Pétrot wrote:
> > On 24/11/2021 07:12, Alistair Francis wrote:
> >> On Sat, Nov 13, 2021 at 1:16 AM Frédéric Pétrot
> >> wrote:
> >>>
> >>> This patch is kind of a mess because several files have to be slightly
> >>> modified to allow for a new target. In the current status, we have done
> >>> our best to have RV64 and RV128 under the same RV64 umbrella, but there
> >>> is still work to do to have a single executable for both.
> >>> In particular, we have no atomic accesses for aligned 128-bit addresses.
> >>>
> >>> Once this patch applied, adding risc128-sofmmu to --target-list produces
> >>> a (no so useful yet) executable.
> >>
> >> I can't remember if we discussed this before, but do we need the
> >> riscv128-sofmmu executable? Can we instead just use a riscv64-sofmmu
> >> executable?
> >
> > Hello Alistair,
> > Richard was also advocating for a single executable, but pointed out that
> > we need to disable mttcg because there is a need for specific tcg
> > support for
> > 128-bit aligned atomics.
> > Given my understanding of that part of QEMU, I choose the easy way to
> > disable
> > it once and for all at compile time until we have that.
>
>
> In rv128_base_cpu_init():
>
> if (qemu_tcg_mttcg_enabled) {
> /* Missing 128-bit aligned atomics */
> error_report("128-bit RISC-V currently does not work"
>" with Multi Threaded TCG. Please use:"
>" -accel tcg,thread=single");
> exit(EXIT_FAILURE);
> }
That seems like a good option! I think we could add this to the CPU
realise function.
The problem with a riscv128-sofmmu executable is that it's hard to get
rid of in the future. We are very slowly moving towards a single
executable and adding a new one means we are stuck with it for a
while.
Alistair
>
> Regards,
>
> Phil.
Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles
Hi Frédéric,
On 11/24/21 07:55, Frédéric Pétrot wrote:
> On 24/11/2021 07:12, Alistair Francis wrote:
>> On Sat, Nov 13, 2021 at 1:16 AM Frédéric Pétrot
>> wrote:
>>>
>>> This patch is kind of a mess because several files have to be slightly
>>> modified to allow for a new target. In the current status, we have done
>>> our best to have RV64 and RV128 under the same RV64 umbrella, but there
>>> is still work to do to have a single executable for both.
>>> In particular, we have no atomic accesses for aligned 128-bit addresses.
>>>
>>> Once this patch applied, adding risc128-sofmmu to --target-list produces
>>> a (no so useful yet) executable.
>>
>> I can't remember if we discussed this before, but do we need the
>> riscv128-sofmmu executable? Can we instead just use a riscv64-sofmmu
>> executable?
>
> Hello Alistair,
> Richard was also advocating for a single executable, but pointed out that
> we need to disable mttcg because there is a need for specific tcg
> support for
> 128-bit aligned atomics.
> Given my understanding of that part of QEMU, I choose the easy way to
> disable
> it once and for all at compile time until we have that.
In rv128_base_cpu_init():
if (qemu_tcg_mttcg_enabled) {
/* Missing 128-bit aligned atomics */
error_report("128-bit RISC-V currently does not work"
" with Multi Threaded TCG. Please use:"
" -accel tcg,thread=single");
exit(EXIT_FAILURE);
}
Regards,
Phil.
Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles
On 24/11/2021 07:12, Alistair Francis wrote: On Sat, Nov 13, 2021 at 1:16 AM Frédéric Pétrot wrote: This patch is kind of a mess because several files have to be slightly modified to allow for a new target. In the current status, we have done our best to have RV64 and RV128 under the same RV64 umbrella, but there is still work to do to have a single executable for both. In particular, we have no atomic accesses for aligned 128-bit addresses. Once this patch applied, adding risc128-sofmmu to --target-list produces a (no so useful yet) executable. I can't remember if we discussed this before, but do we need the riscv128-sofmmu executable? Can we instead just use a riscv64-sofmmu executable? Hello Alistair, Richard was also advocating for a single executable, but pointed out that we need to disable mttcg because there is a need for specific tcg support for 128-bit aligned atomics. Given my understanding of that part of QEMU, I choose the easy way to disable it once and for all at compile time until we have that. Frédéric Alistair Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- configs/devices/riscv128-softmmu/default.mak | 17 +++ configs/targets/riscv128-softmmu.mak | 6 ++ include/disas/dis-asm.h | 1 + include/hw/riscv/sifive_cpu.h| 3 +++ target/riscv/cpu-param.h | 5 + target/riscv/cpu.h | 3 +++ disas/riscv.c| 5 + target/riscv/cpu.c | 22 ++-- target/riscv/gdbstub.c | 8 +++ target/riscv/insn_trans/trans_rvd.c.inc | 12 +-- target/riscv/insn_trans/trans_rvf.c.inc | 6 +++--- target/riscv/Kconfig | 3 +++ 12 files changed, 80 insertions(+), 11 deletions(-) create mode 100644 configs/devices/riscv128-softmmu/default.mak create mode 100644 configs/targets/riscv128-softmmu.mak diff --git a/configs/devices/riscv128-softmmu/default.mak b/configs/devices/riscv128-softmmu/default.mak new file mode 100644 index 00..e838f35785 --- /dev/null +++ b/configs/devices/riscv128-softmmu/default.mak @@ -0,0 +1,17 @@ +# Default configuration for riscv128-softmmu + +# Uncomment the following lines to disable these optional devices: +# +#CONFIG_PCI_DEVICES=n +# No does not seem to be an option for these two parameters +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y + +# Boards: +# +CONFIG_SPIKE=n +CONFIG_SIFIVE_E=n +CONFIG_SIFIVE_U=n +CONFIG_RISCV_VIRT=y +CONFIG_MICROCHIP_PFSOC=n +CONFIG_SHAKTI_C=n diff --git a/configs/targets/riscv128-softmmu.mak b/configs/targets/riscv128-softmmu.mak new file mode 100644 index 00..d812cc1c80 --- /dev/null +++ b/configs/targets/riscv128-softmmu.mak @@ -0,0 +1,6 @@ +TARGET_ARCH=riscv128 +TARGET_BASE_ARCH=riscv +# As long as we have no atomic accesses for aligned 128-bit addresses +TARGET_SUPPORTS_MTTCG=n +TARGET_XML_FILES=gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml +TARGET_NEED_FDT=y diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index 08e1beec85..102a1e7f50 100644 --- a/include/disas/dis-asm.h +++ b/include/disas/dis-asm.h @@ -459,6 +459,7 @@ int print_insn_nios2(bfd_vma, disassemble_info*); int print_insn_xtensa (bfd_vma, disassemble_info*); int print_insn_riscv32 (bfd_vma, disassemble_info*); int print_insn_riscv64 (bfd_vma, disassemble_info*); +int print_insn_riscv128 (bfd_vma, disassemble_info*); int print_insn_rx(bfd_vma, disassemble_info *); int print_insn_hexagon(bfd_vma, disassemble_info *); diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h index 136799633a..64078feba8 100644 --- a/include/hw/riscv/sifive_cpu.h +++ b/include/hw/riscv/sifive_cpu.h @@ -26,6 +26,9 @@ #elif defined(TARGET_RISCV64) #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 +#else +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 #endif #endif /* HW_SIFIVE_CPU_H */ diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index 80eb615f93..c10459b56f 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -16,6 +16,11 @@ # define TARGET_LONG_BITS 32 # define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ +#else +/* 64-bit target, since QEMU isn't built to have TARGET_LONG_BITS over 64 */ +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ +# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ /* diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 53a295efb7..8ff5b08d15 100644 --- a/target/riscv/cpu.h +++
Re: [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles
On Sat, Nov 13, 2021 at 1:16 AM Frédéric Pétrot
wrote:
>
> This patch is kind of a mess because several files have to be slightly
> modified to allow for a new target. In the current status, we have done
> our best to have RV64 and RV128 under the same RV64 umbrella, but there
> is still work to do to have a single executable for both.
> In particular, we have no atomic accesses for aligned 128-bit addresses.
>
> Once this patch applied, adding risc128-sofmmu to --target-list produces
> a (no so useful yet) executable.
I can't remember if we discussed this before, but do we need the
riscv128-sofmmu executable? Can we instead just use a riscv64-sofmmu
executable?
Alistair
>
> Signed-off-by: Frédéric Pétrot
> Co-authored-by: Fabien Portas
> ---
> configs/devices/riscv128-softmmu/default.mak | 17 +++
> configs/targets/riscv128-softmmu.mak | 6 ++
> include/disas/dis-asm.h | 1 +
> include/hw/riscv/sifive_cpu.h| 3 +++
> target/riscv/cpu-param.h | 5 +
> target/riscv/cpu.h | 3 +++
> disas/riscv.c| 5 +
> target/riscv/cpu.c | 22 ++--
> target/riscv/gdbstub.c | 8 +++
> target/riscv/insn_trans/trans_rvd.c.inc | 12 +--
> target/riscv/insn_trans/trans_rvf.c.inc | 6 +++---
> target/riscv/Kconfig | 3 +++
> 12 files changed, 80 insertions(+), 11 deletions(-)
> create mode 100644 configs/devices/riscv128-softmmu/default.mak
> create mode 100644 configs/targets/riscv128-softmmu.mak
>
> diff --git a/configs/devices/riscv128-softmmu/default.mak
> b/configs/devices/riscv128-softmmu/default.mak
> new file mode 100644
> index 00..e838f35785
> --- /dev/null
> +++ b/configs/devices/riscv128-softmmu/default.mak
> @@ -0,0 +1,17 @@
> +# Default configuration for riscv128-softmmu
> +
> +# Uncomment the following lines to disable these optional devices:
> +#
> +#CONFIG_PCI_DEVICES=n
> +# No does not seem to be an option for these two parameters
> +CONFIG_SEMIHOSTING=y
> +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
> +
> +# Boards:
> +#
> +CONFIG_SPIKE=n
> +CONFIG_SIFIVE_E=n
> +CONFIG_SIFIVE_U=n
> +CONFIG_RISCV_VIRT=y
> +CONFIG_MICROCHIP_PFSOC=n
> +CONFIG_SHAKTI_C=n
> diff --git a/configs/targets/riscv128-softmmu.mak
> b/configs/targets/riscv128-softmmu.mak
> new file mode 100644
> index 00..d812cc1c80
> --- /dev/null
> +++ b/configs/targets/riscv128-softmmu.mak
> @@ -0,0 +1,6 @@
> +TARGET_ARCH=riscv128
> +TARGET_BASE_ARCH=riscv
> +# As long as we have no atomic accesses for aligned 128-bit addresses
> +TARGET_SUPPORTS_MTTCG=n
> +TARGET_XML_FILES=gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml
> gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
> +TARGET_NEED_FDT=y
> diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
> index 08e1beec85..102a1e7f50 100644
> --- a/include/disas/dis-asm.h
> +++ b/include/disas/dis-asm.h
> @@ -459,6 +459,7 @@ int print_insn_nios2(bfd_vma, disassemble_info*);
> int print_insn_xtensa (bfd_vma, disassemble_info*);
> int print_insn_riscv32 (bfd_vma, disassemble_info*);
> int print_insn_riscv64 (bfd_vma, disassemble_info*);
> +int print_insn_riscv128 (bfd_vma, disassemble_info*);
> int print_insn_rx(bfd_vma, disassemble_info *);
> int print_insn_hexagon(bfd_vma, disassemble_info *);
>
> diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
> index 136799633a..64078feba8 100644
> --- a/include/hw/riscv/sifive_cpu.h
> +++ b/include/hw/riscv/sifive_cpu.h
> @@ -26,6 +26,9 @@
> #elif defined(TARGET_RISCV64)
> #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
> #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
> +#else
> +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
> +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
> #endif
>
> #endif /* HW_SIFIVE_CPU_H */
> diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
> index 80eb615f93..c10459b56f 100644
> --- a/target/riscv/cpu-param.h
> +++ b/target/riscv/cpu-param.h
> @@ -16,6 +16,11 @@
> # define TARGET_LONG_BITS 32
> # define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
> # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
> +#else
> +/* 64-bit target, since QEMU isn't built to have TARGET_LONG_BITS over 64 */
> +# define TARGET_LONG_BITS 64
> +# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
> +# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
> #endif
> #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
> /*
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 53a295efb7..8ff5b08d15 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -38,6 +38,7 @@
> #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64
[PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles
This patch is kind of a mess because several files have to be slightly
modified to allow for a new target. In the current status, we have done
our best to have RV64 and RV128 under the same RV64 umbrella, but there
is still work to do to have a single executable for both.
In particular, we have no atomic accesses for aligned 128-bit addresses.
Once this patch applied, adding risc128-sofmmu to --target-list produces
a (no so useful yet) executable.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
configs/devices/riscv128-softmmu/default.mak | 17 +++
configs/targets/riscv128-softmmu.mak | 6 ++
include/disas/dis-asm.h | 1 +
include/hw/riscv/sifive_cpu.h| 3 +++
target/riscv/cpu-param.h | 5 +
target/riscv/cpu.h | 3 +++
disas/riscv.c| 5 +
target/riscv/cpu.c | 22 ++--
target/riscv/gdbstub.c | 8 +++
target/riscv/insn_trans/trans_rvd.c.inc | 12 +--
target/riscv/insn_trans/trans_rvf.c.inc | 6 +++---
target/riscv/Kconfig | 3 +++
12 files changed, 80 insertions(+), 11 deletions(-)
create mode 100644 configs/devices/riscv128-softmmu/default.mak
create mode 100644 configs/targets/riscv128-softmmu.mak
diff --git a/configs/devices/riscv128-softmmu/default.mak
b/configs/devices/riscv128-softmmu/default.mak
new file mode 100644
index 00..e838f35785
--- /dev/null
+++ b/configs/devices/riscv128-softmmu/default.mak
@@ -0,0 +1,17 @@
+# Default configuration for riscv128-softmmu
+
+# Uncomment the following lines to disable these optional devices:
+#
+#CONFIG_PCI_DEVICES=n
+# No does not seem to be an option for these two parameters
+CONFIG_SEMIHOSTING=y
+CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+
+# Boards:
+#
+CONFIG_SPIKE=n
+CONFIG_SIFIVE_E=n
+CONFIG_SIFIVE_U=n
+CONFIG_RISCV_VIRT=y
+CONFIG_MICROCHIP_PFSOC=n
+CONFIG_SHAKTI_C=n
diff --git a/configs/targets/riscv128-softmmu.mak
b/configs/targets/riscv128-softmmu.mak
new file mode 100644
index 00..d812cc1c80
--- /dev/null
+++ b/configs/targets/riscv128-softmmu.mak
@@ -0,0 +1,6 @@
+TARGET_ARCH=riscv128
+TARGET_BASE_ARCH=riscv
+# As long as we have no atomic accesses for aligned 128-bit addresses
+TARGET_SUPPORTS_MTTCG=n
+TARGET_XML_FILES=gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml
gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
+TARGET_NEED_FDT=y
diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
index 08e1beec85..102a1e7f50 100644
--- a/include/disas/dis-asm.h
+++ b/include/disas/dis-asm.h
@@ -459,6 +459,7 @@ int print_insn_nios2(bfd_vma, disassemble_info*);
int print_insn_xtensa (bfd_vma, disassemble_info*);
int print_insn_riscv32 (bfd_vma, disassemble_info*);
int print_insn_riscv64 (bfd_vma, disassemble_info*);
+int print_insn_riscv128 (bfd_vma, disassemble_info*);
int print_insn_rx(bfd_vma, disassemble_info *);
int print_insn_hexagon(bfd_vma, disassemble_info *);
diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
index 136799633a..64078feba8 100644
--- a/include/hw/riscv/sifive_cpu.h
+++ b/include/hw/riscv/sifive_cpu.h
@@ -26,6 +26,9 @@
#elif defined(TARGET_RISCV64)
#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
+#else
+#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
+#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
#endif
#endif /* HW_SIFIVE_CPU_H */
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index 80eb615f93..c10459b56f 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -16,6 +16,11 @@
# define TARGET_LONG_BITS 32
# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
+#else
+/* 64-bit target, since QEMU isn't built to have TARGET_LONG_BITS over 64 */
+# define TARGET_LONG_BITS 64
+# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
+# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
/*
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 53a295efb7..8ff5b08d15 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -38,6 +38,7 @@
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
+#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("rv128")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
@@ -50,6 +51,8 @@
# define TYPE_RISCV_CPU_BASETYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
# define
