Re: [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns

2021-05-17 Thread David Gibson 
On Mon, May 17, 2021 at 05:50:13PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Richard Henderson 
> 
> Signed-off-by: Luis Pires 
> Signed-off-by: Richard Henderson 
> Signed-off-by: Matheus Ferst 

Applied to ppc-for-6.1, thanks.

> ---
>  target/ppc/cpu.h   |  1 +
>  target/ppc/insn32.decode   | 18 
>  target/ppc/insn64.decode   | 18 
>  target/ppc/meson.build |  9 ++
>  target/ppc/translate.c | 34 +++---
>  target/ppc/translate/fixedpoint-impl.c.inc | 18 
>  6 files changed, 94 insertions(+), 4 deletions(-)
>  create mode 100644 target/ppc/insn32.decode
>  create mode 100644 target/ppc/insn64.decode
>  create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index cab33a3680..351fcdf5f8 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -144,6 +144,7 @@ enum {
>  POWERPC_EXCP_ALIGN_PROT= 0x04,  /* Access cross protection boundary  
> */
>  POWERPC_EXCP_ALIGN_BAT = 0x05,  /* Access cross a BAT/seg boundary   
> */
>  POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access
> */
> +POWERPC_EXCP_ALIGN_INSN= 0x07,  /* Pref. insn x-ing 64-byte boundary 
> */
>  /* Exception subtypes for POWERPC_EXCP_PROGRAM   
> */
>  /* FP exceptions 
> */
>  POWERPC_EXCP_FP= 0x10,
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> new file mode 100644
> index 00..a3a8ae06bf
> --- /dev/null
> +++ b/target/ppc/insn32.decode
> @@ -0,0 +1,18 @@
> +#
> +# Power ISA decode for 32-bit insns (opcode space 0)
> +#
> +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
> +#
> +# This library is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU Lesser General Public
> +# License as published by the Free Software Foundation; either
> +# version 2.1 of the License, or (at your option) any later version.
> +#
> +# This library is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> +# Lesser General Public License for more details.
> +#
> +# You should have received a copy of the GNU Lesser General Public
> +# License along with this library; if not, see 
> .
> +#
> diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
> new file mode 100644
> index 00..a38b1f84dc
> --- /dev/null
> +++ b/target/ppc/insn64.decode
> @@ -0,0 +1,18 @@
> +#
> +# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1)
> +#
> +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
> +#
> +# This library is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU Lesser General Public
> +# License as published by the Free Software Foundation; either
> +# version 2.1 of the License, or (at your option) any later version.
> +#
> +# This library is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> +# Lesser General Public License for more details.
> +#
> +# You should have received a copy of the GNU Lesser General Public
> +# License along with this library; if not, see 
> .
> +#
> diff --git a/target/ppc/meson.build b/target/ppc/meson.build
> index d1aa7d5d39..512e3a0288 100644
> --- a/target/ppc/meson.build
> +++ b/target/ppc/meson.build
> @@ -17,6 +17,15 @@ ppc_ss.add(files(
>  
>  ppc_ss.add(libdecnumber)
>  
> +gen = [
> +  decodetree.process('insn32.decode',
> + extra_args: '--static-decode=decode_insn32'),
> +  decodetree.process('insn64.decode',
> + extra_args: ['--static-decode=decode_insn64',
> +  '--insnwidth=64']),
> +]
> +ppc_ss.add(gen)
> +
>  ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: 
> files('kvm-stub.c'))
>  ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c'))
>  
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index b1873d2dcc..64d6acb078 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7776,6 +7776,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, 
> bool high)
>  # define REQUIRE_64BIT(CTX)  REQUIRE_INSNS_FLAGS(CTX, 64B)
>  #endif
>  
> +#include "decode-insn32.c.inc"
> +#include "decode-insn64.c.inc"
> +#include "translate/fixedpoint-impl.c.inc"
> +
>  #include "translate/fp-impl.c.inc"
>  
>  #include "translate/vmx-impl.c.inc"
> @@ -9089,11 +9093,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase 
>

[PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns

2021-05-17 Thread matheus . ferst 
From: Richard Henderson 

Signed-off-by: Luis Pires 
Signed-off-by: Richard Henderson 
Signed-off-by: Matheus Ferst 
---
 target/ppc/cpu.h   |  1 +
 target/ppc/insn32.decode   | 18 
 target/ppc/insn64.decode   | 18 
 target/ppc/meson.build |  9 ++
 target/ppc/translate.c | 34 +++---
 target/ppc/translate/fixedpoint-impl.c.inc | 18 
 6 files changed, 94 insertions(+), 4 deletions(-)
 create mode 100644 target/ppc/insn32.decode
 create mode 100644 target/ppc/insn64.decode
 create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cab33a3680..351fcdf5f8 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -144,6 +144,7 @@ enum {
 POWERPC_EXCP_ALIGN_PROT= 0x04,  /* Access cross protection boundary  */
 POWERPC_EXCP_ALIGN_BAT = 0x05,  /* Access cross a BAT/seg boundary   */
 POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access*/
+POWERPC_EXCP_ALIGN_INSN= 0x07,  /* Pref. insn x-ing 64-byte boundary */
 /* Exception subtypes for POWERPC_EXCP_PROGRAM   */
 /* FP exceptions */
 POWERPC_EXCP_FP= 0x10,
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
new file mode 100644
index 00..a3a8ae06bf
--- /dev/null
+++ b/target/ppc/insn32.decode
@@ -0,0 +1,18 @@
+#
+# Power ISA decode for 32-bit insns (opcode space 0)
+#
+# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see .
+#
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
new file mode 100644
index 00..a38b1f84dc
--- /dev/null
+++ b/target/ppc/insn64.decode
@@ -0,0 +1,18 @@
+#
+# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1)
+#
+# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see .
+#
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
index d1aa7d5d39..512e3a0288 100644
--- a/target/ppc/meson.build
+++ b/target/ppc/meson.build
@@ -17,6 +17,15 @@ ppc_ss.add(files(
 
 ppc_ss.add(libdecnumber)
 
+gen = [
+  decodetree.process('insn32.decode',
+ extra_args: '--static-decode=decode_insn32'),
+  decodetree.process('insn64.decode',
+ extra_args: ['--static-decode=decode_insn64',
+  '--insnwidth=64']),
+]
+ppc_ss.add(gen)
+
 ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: 
files('kvm-stub.c'))
 ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c'))
 
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b1873d2dcc..64d6acb078 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7776,6 +7776,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, 
bool high)
 # define REQUIRE_64BIT(CTX)  REQUIRE_INSNS_FLAGS(CTX, 64B)
 #endif
 
+#include "decode-insn32.c.inc"
+#include "decode-insn64.c.inc"
+#include "translate/fixedpoint-impl.c.inc"
+
 #include "translate/fp-impl.c.inc"
 
 #include "translate/vmx-impl.c.inc"
@@ -9089,11 +9093,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase 
*dcbase, CPUState *cs,
 return true;
 }
 
+static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
+{
+REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+return opc1(insn) == 1;
+}
+
 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
 {
 DisasContext *ctx = container_of(dcbase, DisasContext, base);
 PowerPCCPU *cpu = POWERPC_CPU(cs);