Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
On Thu, Jul 21, 2022 at 5:32 AM Atish Patra wrote:
>
> On Wed, Jun 15, 2022 at 8:25 PM Anup Patel wrote:
> >
> > On Thu, Jun 16, 2022 at 8:08 AM Alistair Francis
> > wrote:
> > >
> > > On Thu, Jun 16, 2022 at 4:21 AM Atish Kumar Patra
> > > wrote:
> > > >
> > > > On Wed, Jun 8, 2022 at 12:19 AM Alistair Francis
> > > > wrote:
> > > > >
> > > > > On Mon, Jun 6, 2022 at 2:23 AM Atish Patra
> > > > > wrote:
> > > > > >
> > > > > > On Thu, Jun 2, 2022 at 12:02 AM Alistair Francis
> > > > > > wrote:
> > > > > > >
> > > > > > > On Wed, Jun 1, 2022 at 4:16 AM Atish Patra
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > stimecmp allows the supervisor mode to update stimecmp CSR
> > > > > > > > directly
> > > > > > > > to program the next timer interrupt. This CSR is part of the
> > > > > > > > Sstc
> > > > > > > > extension which was ratified recently.
> > > > > > > >
> > > > > > > > Signed-off-by: Atish Patra
> > > > > > > > ---
> > > > > > > > target/riscv/cpu.c | 8
> > > > > > > > target/riscv/cpu.h | 5 ++
> > > > > > > > target/riscv/cpu_bits.h| 4 ++
> > > > > > > > target/riscv/csr.c | 81 +++
> > > > > > > > target/riscv/machine.c | 1 +
> > > > > > > > target/riscv/meson.build | 3 +-
> > > > > > > > target/riscv/time_helper.c | 98
> > > > > > > > ++
> > > > > > > > target/riscv/time_helper.h | 30
> > > > > > > > 8 files changed, 229 insertions(+), 1 deletion(-)
> > > > > > > > create mode 100644 target/riscv/time_helper.c
> > > > > > > > create mode 100644 target/riscv/time_helper.h
> > > > > > > >
> > > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > > > > > > index 19f4e8294042..d58dd2f857a7 100644
> > > > > > > > --- a/target/riscv/cpu.c
> > > > > > > > +++ b/target/riscv/cpu.c
> > > > > > > > @@ -23,6 +23,7 @@
> > > > > > > > #include "qemu/log.h"
> > > > > > > > #include "cpu.h"
> > > > > > > > #include "internals.h"
> > > > > > > > +#include "time_helper.h"
> > > > > > > > #include "exec/exec-all.h"
> > > > > > > > #include "qapi/error.h"
> > > > > > > > #include "qemu/error-report.h"
> > > > > > > > @@ -779,7 +780,12 @@ static void riscv_cpu_init(Object *obj)
> > > > > > > > #ifndef CONFIG_USER_ONLY
> > > > > > > > qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
> > > > > > > >IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> > > > > > > > +
> > > > > > > > +if (cpu->cfg.ext_sstc) {
> > > > > > > > +riscv_timer_init(cpu);
> > > > > > > > +}
> > > > > > > > #endif /* CONFIG_USER_ONLY */
> > > > > > > > +
> > > > > > > > }
> > > > > > > >
> > > > > > > > static Property riscv_cpu_properties[] = {
> > > > > > > > @@ -806,6 +812,7 @@ static Property riscv_cpu_properties[] = {
> > > > > > > > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> > > > > > > > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> > > > > > > > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> > > > > > > > +DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
> > > > > > >
> > > > > > > Do we want this enabled by default?
> > > > > > >
> > > > > >
> > > > > > sstc extension will result in performance improvements as it avoids
> > > > > > the SBI calls & interrupt forwarding
> > > > > > path. That's why I think it should be enabled by default.
> > > > > >
> > > > > > > >
> > > > > > > > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> > > > > > > > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> > > > > > > > @@ -965,6 +972,7 @@ static void riscv_isa_string_ext(RISCVCPU
> > > > > > > > *cpu, char **isa_str, int max_str_len)
> > > > > > > > ISA_EDATA_ENTRY(zbs, ext_zbs),
> > > > > > > > ISA_EDATA_ENTRY(zve32f, ext_zve32f),
> > > > > > > > ISA_EDATA_ENTRY(zve64f, ext_zve64f),
> > > > > > > > +ISA_EDATA_ENTRY(sstc, ext_sstc),
> > > > > > > > ISA_EDATA_ENTRY(svinval, ext_svinval),
> > > > > > > > ISA_EDATA_ENTRY(svnapot, ext_svnapot),
> > > > > > > > ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
> > > > > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > > > > > > index 1119d5201066..9a5e02f217ba 100644
> > > > > > > > --- a/target/riscv/cpu.h
> > > > > > > > +++ b/target/riscv/cpu.h
> > > > > > > > @@ -276,6 +276,9 @@ struct CPUArchState {
> > > > > > > > uint64_t mfromhost;
> > > > > > > > uint64_t mtohost;
> > > > > > > >
> > > > > > > > +/* Sstc CSRs */
> > > > > > > > +uint64_t stimecmp;
> > > > > > > > +
> > > > > > > > /* physical memory protection */
> > > > > > > > pmp_table_t pmp_state;
> > > > > > > > target_ulong mseccfg;
> > > > > > > > @@ -329,6 +332,7 @@ struct CPUArchState {
> > > > > > > > float_status fp_status;
> > > > > > > >
> > > > > > > > /* Fields from here on are preserved across CPU reset. */
> > > > > > > > +
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
On Wed, Jun 15, 2022 at 8:25 PM Anup Patel wrote:
>
> On Thu, Jun 16, 2022 at 8:08 AM Alistair Francis wrote:
> >
> > On Thu, Jun 16, 2022 at 4:21 AM Atish Kumar Patra
> > wrote:
> > >
> > > On Wed, Jun 8, 2022 at 12:19 AM Alistair Francis
> > > wrote:
> > > >
> > > > On Mon, Jun 6, 2022 at 2:23 AM Atish Patra
> > > > wrote:
> > > > >
> > > > > On Thu, Jun 2, 2022 at 12:02 AM Alistair Francis
> > > > > wrote:
> > > > > >
> > > > > > On Wed, Jun 1, 2022 at 4:16 AM Atish Patra
> > > > > > wrote:
> > > > > > >
> > > > > > > stimecmp allows the supervisor mode to update stimecmp CSR
> > > > > > > directly
> > > > > > > to program the next timer interrupt. This CSR is part of the Sstc
> > > > > > > extension which was ratified recently.
> > > > > > >
> > > > > > > Signed-off-by: Atish Patra
> > > > > > > ---
> > > > > > > target/riscv/cpu.c | 8
> > > > > > > target/riscv/cpu.h | 5 ++
> > > > > > > target/riscv/cpu_bits.h| 4 ++
> > > > > > > target/riscv/csr.c | 81 +++
> > > > > > > target/riscv/machine.c | 1 +
> > > > > > > target/riscv/meson.build | 3 +-
> > > > > > > target/riscv/time_helper.c | 98
> > > > > > > ++
> > > > > > > target/riscv/time_helper.h | 30
> > > > > > > 8 files changed, 229 insertions(+), 1 deletion(-)
> > > > > > > create mode 100644 target/riscv/time_helper.c
> > > > > > > create mode 100644 target/riscv/time_helper.h
> > > > > > >
> > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > > > > > index 19f4e8294042..d58dd2f857a7 100644
> > > > > > > --- a/target/riscv/cpu.c
> > > > > > > +++ b/target/riscv/cpu.c
> > > > > > > @@ -23,6 +23,7 @@
> > > > > > > #include "qemu/log.h"
> > > > > > > #include "cpu.h"
> > > > > > > #include "internals.h"
> > > > > > > +#include "time_helper.h"
> > > > > > > #include "exec/exec-all.h"
> > > > > > > #include "qapi/error.h"
> > > > > > > #include "qemu/error-report.h"
> > > > > > > @@ -779,7 +780,12 @@ static void riscv_cpu_init(Object *obj)
> > > > > > > #ifndef CONFIG_USER_ONLY
> > > > > > > qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
> > > > > > >IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> > > > > > > +
> > > > > > > +if (cpu->cfg.ext_sstc) {
> > > > > > > +riscv_timer_init(cpu);
> > > > > > > +}
> > > > > > > #endif /* CONFIG_USER_ONLY */
> > > > > > > +
> > > > > > > }
> > > > > > >
> > > > > > > static Property riscv_cpu_properties[] = {
> > > > > > > @@ -806,6 +812,7 @@ static Property riscv_cpu_properties[] = {
> > > > > > > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> > > > > > > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> > > > > > > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> > > > > > > +DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
> > > > > >
> > > > > > Do we want this enabled by default?
> > > > > >
> > > > >
> > > > > sstc extension will result in performance improvements as it avoids
> > > > > the SBI calls & interrupt forwarding
> > > > > path. That's why I think it should be enabled by default.
> > > > >
> > > > > > >
> > > > > > > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> > > > > > > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> > > > > > > @@ -965,6 +972,7 @@ static void riscv_isa_string_ext(RISCVCPU
> > > > > > > *cpu, char **isa_str, int max_str_len)
> > > > > > > ISA_EDATA_ENTRY(zbs, ext_zbs),
> > > > > > > ISA_EDATA_ENTRY(zve32f, ext_zve32f),
> > > > > > > ISA_EDATA_ENTRY(zve64f, ext_zve64f),
> > > > > > > +ISA_EDATA_ENTRY(sstc, ext_sstc),
> > > > > > > ISA_EDATA_ENTRY(svinval, ext_svinval),
> > > > > > > ISA_EDATA_ENTRY(svnapot, ext_svnapot),
> > > > > > > ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
> > > > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > > > > > index 1119d5201066..9a5e02f217ba 100644
> > > > > > > --- a/target/riscv/cpu.h
> > > > > > > +++ b/target/riscv/cpu.h
> > > > > > > @@ -276,6 +276,9 @@ struct CPUArchState {
> > > > > > > uint64_t mfromhost;
> > > > > > > uint64_t mtohost;
> > > > > > >
> > > > > > > +/* Sstc CSRs */
> > > > > > > +uint64_t stimecmp;
> > > > > > > +
> > > > > > > /* physical memory protection */
> > > > > > > pmp_table_t pmp_state;
> > > > > > > target_ulong mseccfg;
> > > > > > > @@ -329,6 +332,7 @@ struct CPUArchState {
> > > > > > > float_status fp_status;
> > > > > > >
> > > > > > > /* Fields from here on are preserved across CPU reset. */
> > > > > > > +QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
> > > > > > >
> > > > > > > hwaddr kernel_addr;
> > > > > > > hwaddr fdt_addr;
> > > > > > > @@ -379,6 +383,7 @@ struct RISCVCPUConfig {
> > > > > > > bool ext_counters;
> > > > > > > bool ext_ifencei;
> > > > > > >
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
On Thu, Jun 16, 2022 at 8:08 AM Alistair Francis wrote:
>
> On Thu, Jun 16, 2022 at 4:21 AM Atish Kumar Patra wrote:
> >
> > On Wed, Jun 8, 2022 at 12:19 AM Alistair Francis
> > wrote:
> > >
> > > On Mon, Jun 6, 2022 at 2:23 AM Atish Patra wrote:
> > > >
> > > > On Thu, Jun 2, 2022 at 12:02 AM Alistair Francis
> > > > wrote:
> > > > >
> > > > > On Wed, Jun 1, 2022 at 4:16 AM Atish Patra
> > > > > wrote:
> > > > > >
> > > > > > stimecmp allows the supervisor mode to update stimecmp CSR directly
> > > > > > to program the next timer interrupt. This CSR is part of the Sstc
> > > > > > extension which was ratified recently.
> > > > > >
> > > > > > Signed-off-by: Atish Patra
> > > > > > ---
> > > > > > target/riscv/cpu.c | 8
> > > > > > target/riscv/cpu.h | 5 ++
> > > > > > target/riscv/cpu_bits.h| 4 ++
> > > > > > target/riscv/csr.c | 81 +++
> > > > > > target/riscv/machine.c | 1 +
> > > > > > target/riscv/meson.build | 3 +-
> > > > > > target/riscv/time_helper.c | 98
> > > > > > ++
> > > > > > target/riscv/time_helper.h | 30
> > > > > > 8 files changed, 229 insertions(+), 1 deletion(-)
> > > > > > create mode 100644 target/riscv/time_helper.c
> > > > > > create mode 100644 target/riscv/time_helper.h
> > > > > >
> > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > > > > index 19f4e8294042..d58dd2f857a7 100644
> > > > > > --- a/target/riscv/cpu.c
> > > > > > +++ b/target/riscv/cpu.c
> > > > > > @@ -23,6 +23,7 @@
> > > > > > #include "qemu/log.h"
> > > > > > #include "cpu.h"
> > > > > > #include "internals.h"
> > > > > > +#include "time_helper.h"
> > > > > > #include "exec/exec-all.h"
> > > > > > #include "qapi/error.h"
> > > > > > #include "qemu/error-report.h"
> > > > > > @@ -779,7 +780,12 @@ static void riscv_cpu_init(Object *obj)
> > > > > > #ifndef CONFIG_USER_ONLY
> > > > > > qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
> > > > > >IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> > > > > > +
> > > > > > +if (cpu->cfg.ext_sstc) {
> > > > > > +riscv_timer_init(cpu);
> > > > > > +}
> > > > > > #endif /* CONFIG_USER_ONLY */
> > > > > > +
> > > > > > }
> > > > > >
> > > > > > static Property riscv_cpu_properties[] = {
> > > > > > @@ -806,6 +812,7 @@ static Property riscv_cpu_properties[] = {
> > > > > > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> > > > > > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> > > > > > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> > > > > > +DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
> > > > >
> > > > > Do we want this enabled by default?
> > > > >
> > > >
> > > > sstc extension will result in performance improvements as it avoids
> > > > the SBI calls & interrupt forwarding
> > > > path. That's why I think it should be enabled by default.
> > > >
> > > > > >
> > > > > > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> > > > > > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> > > > > > @@ -965,6 +972,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu,
> > > > > > char **isa_str, int max_str_len)
> > > > > > ISA_EDATA_ENTRY(zbs, ext_zbs),
> > > > > > ISA_EDATA_ENTRY(zve32f, ext_zve32f),
> > > > > > ISA_EDATA_ENTRY(zve64f, ext_zve64f),
> > > > > > +ISA_EDATA_ENTRY(sstc, ext_sstc),
> > > > > > ISA_EDATA_ENTRY(svinval, ext_svinval),
> > > > > > ISA_EDATA_ENTRY(svnapot, ext_svnapot),
> > > > > > ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
> > > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > > > > index 1119d5201066..9a5e02f217ba 100644
> > > > > > --- a/target/riscv/cpu.h
> > > > > > +++ b/target/riscv/cpu.h
> > > > > > @@ -276,6 +276,9 @@ struct CPUArchState {
> > > > > > uint64_t mfromhost;
> > > > > > uint64_t mtohost;
> > > > > >
> > > > > > +/* Sstc CSRs */
> > > > > > +uint64_t stimecmp;
> > > > > > +
> > > > > > /* physical memory protection */
> > > > > > pmp_table_t pmp_state;
> > > > > > target_ulong mseccfg;
> > > > > > @@ -329,6 +332,7 @@ struct CPUArchState {
> > > > > > float_status fp_status;
> > > > > >
> > > > > > /* Fields from here on are preserved across CPU reset. */
> > > > > > +QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
> > > > > >
> > > > > > hwaddr kernel_addr;
> > > > > > hwaddr fdt_addr;
> > > > > > @@ -379,6 +383,7 @@ struct RISCVCPUConfig {
> > > > > > bool ext_counters;
> > > > > > bool ext_ifencei;
> > > > > > bool ext_icsr;
> > > > > > +bool ext_sstc;
> > > > > > bool ext_svinval;
> > > > > > bool ext_svnapot;
> > > > > > bool ext_svpbmt;
> > > > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > > > > > index 4e5b630f5965..29d0e4a1be01 100644
> > > > > > ---
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
On Thu, Jun 16, 2022 at 4:21 AM Atish Kumar Patra wrote:
>
> On Wed, Jun 8, 2022 at 12:19 AM Alistair Francis wrote:
> >
> > On Mon, Jun 6, 2022 at 2:23 AM Atish Patra wrote:
> > >
> > > On Thu, Jun 2, 2022 at 12:02 AM Alistair Francis
> > > wrote:
> > > >
> > > > On Wed, Jun 1, 2022 at 4:16 AM Atish Patra wrote:
> > > > >
> > > > > stimecmp allows the supervisor mode to update stimecmp CSR directly
> > > > > to program the next timer interrupt. This CSR is part of the Sstc
> > > > > extension which was ratified recently.
> > > > >
> > > > > Signed-off-by: Atish Patra
> > > > > ---
> > > > > target/riscv/cpu.c | 8
> > > > > target/riscv/cpu.h | 5 ++
> > > > > target/riscv/cpu_bits.h| 4 ++
> > > > > target/riscv/csr.c | 81 +++
> > > > > target/riscv/machine.c | 1 +
> > > > > target/riscv/meson.build | 3 +-
> > > > > target/riscv/time_helper.c | 98
> > > > > ++
> > > > > target/riscv/time_helper.h | 30
> > > > > 8 files changed, 229 insertions(+), 1 deletion(-)
> > > > > create mode 100644 target/riscv/time_helper.c
> > > > > create mode 100644 target/riscv/time_helper.h
> > > > >
> > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > > > index 19f4e8294042..d58dd2f857a7 100644
> > > > > --- a/target/riscv/cpu.c
> > > > > +++ b/target/riscv/cpu.c
> > > > > @@ -23,6 +23,7 @@
> > > > > #include "qemu/log.h"
> > > > > #include "cpu.h"
> > > > > #include "internals.h"
> > > > > +#include "time_helper.h"
> > > > > #include "exec/exec-all.h"
> > > > > #include "qapi/error.h"
> > > > > #include "qemu/error-report.h"
> > > > > @@ -779,7 +780,12 @@ static void riscv_cpu_init(Object *obj)
> > > > > #ifndef CONFIG_USER_ONLY
> > > > > qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
> > > > >IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> > > > > +
> > > > > +if (cpu->cfg.ext_sstc) {
> > > > > +riscv_timer_init(cpu);
> > > > > +}
> > > > > #endif /* CONFIG_USER_ONLY */
> > > > > +
> > > > > }
> > > > >
> > > > > static Property riscv_cpu_properties[] = {
> > > > > @@ -806,6 +812,7 @@ static Property riscv_cpu_properties[] = {
> > > > > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> > > > > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> > > > > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> > > > > +DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
> > > >
> > > > Do we want this enabled by default?
> > > >
> > >
> > > sstc extension will result in performance improvements as it avoids
> > > the SBI calls & interrupt forwarding
> > > path. That's why I think it should be enabled by default.
> > >
> > > > >
> > > > > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> > > > > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> > > > > @@ -965,6 +972,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu,
> > > > > char **isa_str, int max_str_len)
> > > > > ISA_EDATA_ENTRY(zbs, ext_zbs),
> > > > > ISA_EDATA_ENTRY(zve32f, ext_zve32f),
> > > > > ISA_EDATA_ENTRY(zve64f, ext_zve64f),
> > > > > +ISA_EDATA_ENTRY(sstc, ext_sstc),
> > > > > ISA_EDATA_ENTRY(svinval, ext_svinval),
> > > > > ISA_EDATA_ENTRY(svnapot, ext_svnapot),
> > > > > ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
> > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > > > index 1119d5201066..9a5e02f217ba 100644
> > > > > --- a/target/riscv/cpu.h
> > > > > +++ b/target/riscv/cpu.h
> > > > > @@ -276,6 +276,9 @@ struct CPUArchState {
> > > > > uint64_t mfromhost;
> > > > > uint64_t mtohost;
> > > > >
> > > > > +/* Sstc CSRs */
> > > > > +uint64_t stimecmp;
> > > > > +
> > > > > /* physical memory protection */
> > > > > pmp_table_t pmp_state;
> > > > > target_ulong mseccfg;
> > > > > @@ -329,6 +332,7 @@ struct CPUArchState {
> > > > > float_status fp_status;
> > > > >
> > > > > /* Fields from here on are preserved across CPU reset. */
> > > > > +QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
> > > > >
> > > > > hwaddr kernel_addr;
> > > > > hwaddr fdt_addr;
> > > > > @@ -379,6 +383,7 @@ struct RISCVCPUConfig {
> > > > > bool ext_counters;
> > > > > bool ext_ifencei;
> > > > > bool ext_icsr;
> > > > > +bool ext_sstc;
> > > > > bool ext_svinval;
> > > > > bool ext_svnapot;
> > > > > bool ext_svpbmt;
> > > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > > > > index 4e5b630f5965..29d0e4a1be01 100644
> > > > > --- a/target/riscv/cpu_bits.h
> > > > > +++ b/target/riscv/cpu_bits.h
> > > > > @@ -215,6 +215,10 @@
> > > > > #define CSR_STVAL 0x143
> > > > > #define CSR_SIP 0x144
> > > > >
> > > > > +/* Sstc supervisor CSRs */
> > > > > +#define CSR_STIMECMP0x14D
> > > > > +#define
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
On Wed, Jun 8, 2022 at 12:19 AM Alistair Francis wrote:
>
> On Mon, Jun 6, 2022 at 2:23 AM Atish Patra wrote:
> >
> > On Thu, Jun 2, 2022 at 12:02 AM Alistair Francis
> > wrote:
> > >
> > > On Wed, Jun 1, 2022 at 4:16 AM Atish Patra wrote:
> > > >
> > > > stimecmp allows the supervisor mode to update stimecmp CSR directly
> > > > to program the next timer interrupt. This CSR is part of the Sstc
> > > > extension which was ratified recently.
> > > >
> > > > Signed-off-by: Atish Patra
> > > > ---
> > > > target/riscv/cpu.c | 8
> > > > target/riscv/cpu.h | 5 ++
> > > > target/riscv/cpu_bits.h| 4 ++
> > > > target/riscv/csr.c | 81 +++
> > > > target/riscv/machine.c | 1 +
> > > > target/riscv/meson.build | 3 +-
> > > > target/riscv/time_helper.c | 98 ++
> > > > target/riscv/time_helper.h | 30
> > > > 8 files changed, 229 insertions(+), 1 deletion(-)
> > > > create mode 100644 target/riscv/time_helper.c
> > > > create mode 100644 target/riscv/time_helper.h
> > > >
> > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > > index 19f4e8294042..d58dd2f857a7 100644
> > > > --- a/target/riscv/cpu.c
> > > > +++ b/target/riscv/cpu.c
> > > > @@ -23,6 +23,7 @@
> > > > #include "qemu/log.h"
> > > > #include "cpu.h"
> > > > #include "internals.h"
> > > > +#include "time_helper.h"
> > > > #include "exec/exec-all.h"
> > > > #include "qapi/error.h"
> > > > #include "qemu/error-report.h"
> > > > @@ -779,7 +780,12 @@ static void riscv_cpu_init(Object *obj)
> > > > #ifndef CONFIG_USER_ONLY
> > > > qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
> > > >IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> > > > +
> > > > +if (cpu->cfg.ext_sstc) {
> > > > +riscv_timer_init(cpu);
> > > > +}
> > > > #endif /* CONFIG_USER_ONLY */
> > > > +
> > > > }
> > > >
> > > > static Property riscv_cpu_properties[] = {
> > > > @@ -806,6 +812,7 @@ static Property riscv_cpu_properties[] = {
> > > > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> > > > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> > > > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> > > > +DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
> > >
> > > Do we want this enabled by default?
> > >
> >
> > sstc extension will result in performance improvements as it avoids
> > the SBI calls & interrupt forwarding
> > path. That's why I think it should be enabled by default.
> >
> > > >
> > > > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> > > > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> > > > @@ -965,6 +972,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu,
> > > > char **isa_str, int max_str_len)
> > > > ISA_EDATA_ENTRY(zbs, ext_zbs),
> > > > ISA_EDATA_ENTRY(zve32f, ext_zve32f),
> > > > ISA_EDATA_ENTRY(zve64f, ext_zve64f),
> > > > +ISA_EDATA_ENTRY(sstc, ext_sstc),
> > > > ISA_EDATA_ENTRY(svinval, ext_svinval),
> > > > ISA_EDATA_ENTRY(svnapot, ext_svnapot),
> > > > ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
> > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > > index 1119d5201066..9a5e02f217ba 100644
> > > > --- a/target/riscv/cpu.h
> > > > +++ b/target/riscv/cpu.h
> > > > @@ -276,6 +276,9 @@ struct CPUArchState {
> > > > uint64_t mfromhost;
> > > > uint64_t mtohost;
> > > >
> > > > +/* Sstc CSRs */
> > > > +uint64_t stimecmp;
> > > > +
> > > > /* physical memory protection */
> > > > pmp_table_t pmp_state;
> > > > target_ulong mseccfg;
> > > > @@ -329,6 +332,7 @@ struct CPUArchState {
> > > > float_status fp_status;
> > > >
> > > > /* Fields from here on are preserved across CPU reset. */
> > > > +QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
> > > >
> > > > hwaddr kernel_addr;
> > > > hwaddr fdt_addr;
> > > > @@ -379,6 +383,7 @@ struct RISCVCPUConfig {
> > > > bool ext_counters;
> > > > bool ext_ifencei;
> > > > bool ext_icsr;
> > > > +bool ext_sstc;
> > > > bool ext_svinval;
> > > > bool ext_svnapot;
> > > > bool ext_svpbmt;
> > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > > > index 4e5b630f5965..29d0e4a1be01 100644
> > > > --- a/target/riscv/cpu_bits.h
> > > > +++ b/target/riscv/cpu_bits.h
> > > > @@ -215,6 +215,10 @@
> > > > #define CSR_STVAL 0x143
> > > > #define CSR_SIP 0x144
> > > >
> > > > +/* Sstc supervisor CSRs */
> > > > +#define CSR_STIMECMP0x14D
> > > > +#define CSR_STIMECMPH 0x15D
> > > > +
> > > > /* Supervisor Protection and Translation */
> > > > #define CSR_SPTBR 0x180
> > > > #define CSR_SATP0x180
> > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > > > index 245f007e66e1..48d07911ae14 100644
> > > > ---
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
On Mon, Jun 6, 2022 at 2:23 AM Atish Patra wrote:
>
> On Thu, Jun 2, 2022 at 12:02 AM Alistair Francis wrote:
> >
> > On Wed, Jun 1, 2022 at 4:16 AM Atish Patra wrote:
> > >
> > > stimecmp allows the supervisor mode to update stimecmp CSR directly
> > > to program the next timer interrupt. This CSR is part of the Sstc
> > > extension which was ratified recently.
> > >
> > > Signed-off-by: Atish Patra
> > > ---
> > > target/riscv/cpu.c | 8
> > > target/riscv/cpu.h | 5 ++
> > > target/riscv/cpu_bits.h| 4 ++
> > > target/riscv/csr.c | 81 +++
> > > target/riscv/machine.c | 1 +
> > > target/riscv/meson.build | 3 +-
> > > target/riscv/time_helper.c | 98 ++
> > > target/riscv/time_helper.h | 30
> > > 8 files changed, 229 insertions(+), 1 deletion(-)
> > > create mode 100644 target/riscv/time_helper.c
> > > create mode 100644 target/riscv/time_helper.h
> > >
> > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > index 19f4e8294042..d58dd2f857a7 100644
> > > --- a/target/riscv/cpu.c
> > > +++ b/target/riscv/cpu.c
> > > @@ -23,6 +23,7 @@
> > > #include "qemu/log.h"
> > > #include "cpu.h"
> > > #include "internals.h"
> > > +#include "time_helper.h"
> > > #include "exec/exec-all.h"
> > > #include "qapi/error.h"
> > > #include "qemu/error-report.h"
> > > @@ -779,7 +780,12 @@ static void riscv_cpu_init(Object *obj)
> > > #ifndef CONFIG_USER_ONLY
> > > qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
> > >IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> > > +
> > > +if (cpu->cfg.ext_sstc) {
> > > +riscv_timer_init(cpu);
> > > +}
> > > #endif /* CONFIG_USER_ONLY */
> > > +
> > > }
> > >
> > > static Property riscv_cpu_properties[] = {
> > > @@ -806,6 +812,7 @@ static Property riscv_cpu_properties[] = {
> > > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> > > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> > > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> > > +DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
> >
> > Do we want this enabled by default?
> >
>
> sstc extension will result in performance improvements as it avoids
> the SBI calls & interrupt forwarding
> path. That's why I think it should be enabled by default.
>
> > >
> > > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> > > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> > > @@ -965,6 +972,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char
> > > **isa_str, int max_str_len)
> > > ISA_EDATA_ENTRY(zbs, ext_zbs),
> > > ISA_EDATA_ENTRY(zve32f, ext_zve32f),
> > > ISA_EDATA_ENTRY(zve64f, ext_zve64f),
> > > +ISA_EDATA_ENTRY(sstc, ext_sstc),
> > > ISA_EDATA_ENTRY(svinval, ext_svinval),
> > > ISA_EDATA_ENTRY(svnapot, ext_svnapot),
> > > ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
> > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > index 1119d5201066..9a5e02f217ba 100644
> > > --- a/target/riscv/cpu.h
> > > +++ b/target/riscv/cpu.h
> > > @@ -276,6 +276,9 @@ struct CPUArchState {
> > > uint64_t mfromhost;
> > > uint64_t mtohost;
> > >
> > > +/* Sstc CSRs */
> > > +uint64_t stimecmp;
> > > +
> > > /* physical memory protection */
> > > pmp_table_t pmp_state;
> > > target_ulong mseccfg;
> > > @@ -329,6 +332,7 @@ struct CPUArchState {
> > > float_status fp_status;
> > >
> > > /* Fields from here on are preserved across CPU reset. */
> > > +QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
> > >
> > > hwaddr kernel_addr;
> > > hwaddr fdt_addr;
> > > @@ -379,6 +383,7 @@ struct RISCVCPUConfig {
> > > bool ext_counters;
> > > bool ext_ifencei;
> > > bool ext_icsr;
> > > +bool ext_sstc;
> > > bool ext_svinval;
> > > bool ext_svnapot;
> > > bool ext_svpbmt;
> > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > > index 4e5b630f5965..29d0e4a1be01 100644
> > > --- a/target/riscv/cpu_bits.h
> > > +++ b/target/riscv/cpu_bits.h
> > > @@ -215,6 +215,10 @@
> > > #define CSR_STVAL 0x143
> > > #define CSR_SIP 0x144
> > >
> > > +/* Sstc supervisor CSRs */
> > > +#define CSR_STIMECMP0x14D
> > > +#define CSR_STIMECMPH 0x15D
> > > +
> > > /* Supervisor Protection and Translation */
> > > #define CSR_SPTBR 0x180
> > > #define CSR_SATP0x180
> > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > > index 245f007e66e1..48d07911ae14 100644
> > > --- a/target/riscv/csr.c
> > > +++ b/target/riscv/csr.c
> > > @@ -21,6 +21,7 @@
> > > #include "qemu/log.h"
> > > #include "qemu/timer.h"
> > > #include "cpu.h"
> > > +#include "time_helper.h"
> > > #include "qemu/main-loop.h"
> > > #include "exec/exec-all.h"
> > > #include "sysemu/cpu-timers.h"
> > > @@ -537,6 +538,76 @@
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
On Thu, Jun 2, 2022 at 12:02 AM Alistair Francis wrote:
>
> On Wed, Jun 1, 2022 at 4:16 AM Atish Patra wrote:
> >
> > stimecmp allows the supervisor mode to update stimecmp CSR directly
> > to program the next timer interrupt. This CSR is part of the Sstc
> > extension which was ratified recently.
> >
> > Signed-off-by: Atish Patra
> > ---
> > target/riscv/cpu.c | 8
> > target/riscv/cpu.h | 5 ++
> > target/riscv/cpu_bits.h| 4 ++
> > target/riscv/csr.c | 81 +++
> > target/riscv/machine.c | 1 +
> > target/riscv/meson.build | 3 +-
> > target/riscv/time_helper.c | 98 ++
> > target/riscv/time_helper.h | 30
> > 8 files changed, 229 insertions(+), 1 deletion(-)
> > create mode 100644 target/riscv/time_helper.c
> > create mode 100644 target/riscv/time_helper.h
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 19f4e8294042..d58dd2f857a7 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -23,6 +23,7 @@
> > #include "qemu/log.h"
> > #include "cpu.h"
> > #include "internals.h"
> > +#include "time_helper.h"
> > #include "exec/exec-all.h"
> > #include "qapi/error.h"
> > #include "qemu/error-report.h"
> > @@ -779,7 +780,12 @@ static void riscv_cpu_init(Object *obj)
> > #ifndef CONFIG_USER_ONLY
> > qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
> >IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> > +
> > +if (cpu->cfg.ext_sstc) {
> > +riscv_timer_init(cpu);
> > +}
> > #endif /* CONFIG_USER_ONLY */
> > +
> > }
> >
> > static Property riscv_cpu_properties[] = {
> > @@ -806,6 +812,7 @@ static Property riscv_cpu_properties[] = {
> > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> > +DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
>
> Do we want this enabled by default?
>
sstc extension will result in performance improvements as it avoids
the SBI calls & interrupt forwarding
path. That's why I think it should be enabled by default.
> >
> > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> > @@ -965,6 +972,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char
> > **isa_str, int max_str_len)
> > ISA_EDATA_ENTRY(zbs, ext_zbs),
> > ISA_EDATA_ENTRY(zve32f, ext_zve32f),
> > ISA_EDATA_ENTRY(zve64f, ext_zve64f),
> > +ISA_EDATA_ENTRY(sstc, ext_sstc),
> > ISA_EDATA_ENTRY(svinval, ext_svinval),
> > ISA_EDATA_ENTRY(svnapot, ext_svnapot),
> > ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 1119d5201066..9a5e02f217ba 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -276,6 +276,9 @@ struct CPUArchState {
> > uint64_t mfromhost;
> > uint64_t mtohost;
> >
> > +/* Sstc CSRs */
> > +uint64_t stimecmp;
> > +
> > /* physical memory protection */
> > pmp_table_t pmp_state;
> > target_ulong mseccfg;
> > @@ -329,6 +332,7 @@ struct CPUArchState {
> > float_status fp_status;
> >
> > /* Fields from here on are preserved across CPU reset. */
> > +QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
> >
> > hwaddr kernel_addr;
> > hwaddr fdt_addr;
> > @@ -379,6 +383,7 @@ struct RISCVCPUConfig {
> > bool ext_counters;
> > bool ext_ifencei;
> > bool ext_icsr;
> > +bool ext_sstc;
> > bool ext_svinval;
> > bool ext_svnapot;
> > bool ext_svpbmt;
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 4e5b630f5965..29d0e4a1be01 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -215,6 +215,10 @@
> > #define CSR_STVAL 0x143
> > #define CSR_SIP 0x144
> >
> > +/* Sstc supervisor CSRs */
> > +#define CSR_STIMECMP0x14D
> > +#define CSR_STIMECMPH 0x15D
> > +
> > /* Supervisor Protection and Translation */
> > #define CSR_SPTBR 0x180
> > #define CSR_SATP0x180
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 245f007e66e1..48d07911ae14 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -21,6 +21,7 @@
> > #include "qemu/log.h"
> > #include "qemu/timer.h"
> > #include "cpu.h"
> > +#include "time_helper.h"
> > #include "qemu/main-loop.h"
> > #include "exec/exec-all.h"
> > #include "sysemu/cpu-timers.h"
> > @@ -537,6 +538,76 @@ static RISCVException read_timeh(CPURISCVState *env,
> > int csrno,
> > return RISCV_EXCP_NONE;
> > }
> >
> > +static RISCVException sstc(CPURISCVState *env, int csrno)
> > +{
> > +CPUState *cs = env_cpu(env);
> > +RISCVCPU *cpu = RISCV_CPU(cs);
> > +
> > +if (!cpu->cfg.ext_sstc ||
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
On Wed, Jun 1, 2022 at 4:16 AM Atish Patra wrote:
>
> stimecmp allows the supervisor mode to update stimecmp CSR directly
> to program the next timer interrupt. This CSR is part of the Sstc
> extension which was ratified recently.
>
> Signed-off-by: Atish Patra
> ---
> target/riscv/cpu.c | 8
> target/riscv/cpu.h | 5 ++
> target/riscv/cpu_bits.h| 4 ++
> target/riscv/csr.c | 81 +++
> target/riscv/machine.c | 1 +
> target/riscv/meson.build | 3 +-
> target/riscv/time_helper.c | 98 ++
> target/riscv/time_helper.h | 30
> 8 files changed, 229 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/time_helper.c
> create mode 100644 target/riscv/time_helper.h
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 19f4e8294042..d58dd2f857a7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -23,6 +23,7 @@
> #include "qemu/log.h"
> #include "cpu.h"
> #include "internals.h"
> +#include "time_helper.h"
> #include "exec/exec-all.h"
> #include "qapi/error.h"
> #include "qemu/error-report.h"
> @@ -779,7 +780,12 @@ static void riscv_cpu_init(Object *obj)
> #ifndef CONFIG_USER_ONLY
> qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
>IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> +
> +if (cpu->cfg.ext_sstc) {
> +riscv_timer_init(cpu);
> +}
> #endif /* CONFIG_USER_ONLY */
> +
> }
>
> static Property riscv_cpu_properties[] = {
> @@ -806,6 +812,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> +DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
Do we want this enabled by default?
>
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> @@ -965,6 +972,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char
> **isa_str, int max_str_len)
> ISA_EDATA_ENTRY(zbs, ext_zbs),
> ISA_EDATA_ENTRY(zve32f, ext_zve32f),
> ISA_EDATA_ENTRY(zve64f, ext_zve64f),
> +ISA_EDATA_ENTRY(sstc, ext_sstc),
> ISA_EDATA_ENTRY(svinval, ext_svinval),
> ISA_EDATA_ENTRY(svnapot, ext_svnapot),
> ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1119d5201066..9a5e02f217ba 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -276,6 +276,9 @@ struct CPUArchState {
> uint64_t mfromhost;
> uint64_t mtohost;
>
> +/* Sstc CSRs */
> +uint64_t stimecmp;
> +
> /* physical memory protection */
> pmp_table_t pmp_state;
> target_ulong mseccfg;
> @@ -329,6 +332,7 @@ struct CPUArchState {
> float_status fp_status;
>
> /* Fields from here on are preserved across CPU reset. */
> +QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
>
> hwaddr kernel_addr;
> hwaddr fdt_addr;
> @@ -379,6 +383,7 @@ struct RISCVCPUConfig {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> +bool ext_sstc;
> bool ext_svinval;
> bool ext_svnapot;
> bool ext_svpbmt;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 4e5b630f5965..29d0e4a1be01 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -215,6 +215,10 @@
> #define CSR_STVAL 0x143
> #define CSR_SIP 0x144
>
> +/* Sstc supervisor CSRs */
> +#define CSR_STIMECMP0x14D
> +#define CSR_STIMECMPH 0x15D
> +
> /* Supervisor Protection and Translation */
> #define CSR_SPTBR 0x180
> #define CSR_SATP0x180
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 245f007e66e1..48d07911ae14 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -21,6 +21,7 @@
> #include "qemu/log.h"
> #include "qemu/timer.h"
> #include "cpu.h"
> +#include "time_helper.h"
> #include "qemu/main-loop.h"
> #include "exec/exec-all.h"
> #include "sysemu/cpu-timers.h"
> @@ -537,6 +538,76 @@ static RISCVException read_timeh(CPURISCVState *env, int
> csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException sstc(CPURISCVState *env, int csrno)
> +{
> +CPUState *cs = env_cpu(env);
> +RISCVCPU *cpu = RISCV_CPU(cs);
> +
> +if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +
> +if (env->priv == PRV_M) {
> +return RISCV_EXCP_NONE;
> +}
> +
> +if (env->priv != PRV_S) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +}
> +
> +/*
> + * No need of separate function for rv32 as menvcfg stores both menvcfg
> + * menvcfgh for RV32.
> + */
> +if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
> + get_field(env->menvcfg, MENVCFG_STCE))) {
> +
[PATCH v5 2/3] target/riscv: Add stimecmp support
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 8
target/riscv/cpu.h | 5 ++
target/riscv/cpu_bits.h| 4 ++
target/riscv/csr.c | 81 +++
target/riscv/machine.c | 1 +
target/riscv/meson.build | 3 +-
target/riscv/time_helper.c | 98 ++
target/riscv/time_helper.h | 30
8 files changed, 229 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/time_helper.c
create mode 100644 target/riscv/time_helper.h
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 19f4e8294042..d58dd2f857a7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -23,6 +23,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "internals.h"
+#include "time_helper.h"
#include "exec/exec-all.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
@@ -779,7 +780,12 @@ static void riscv_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
+
+if (cpu->cfg.ext_sstc) {
+riscv_timer_init(cpu);
+}
#endif /* CONFIG_USER_ONLY */
+
}
static Property riscv_cpu_properties[] = {
@@ -806,6 +812,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
+DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
@@ -965,6 +972,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char
**isa_str, int max_str_len)
ISA_EDATA_ENTRY(zbs, ext_zbs),
ISA_EDATA_ENTRY(zve32f, ext_zve32f),
ISA_EDATA_ENTRY(zve64f, ext_zve64f),
+ISA_EDATA_ENTRY(sstc, ext_sstc),
ISA_EDATA_ENTRY(svinval, ext_svinval),
ISA_EDATA_ENTRY(svnapot, ext_svnapot),
ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1119d5201066..9a5e02f217ba 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -276,6 +276,9 @@ struct CPUArchState {
uint64_t mfromhost;
uint64_t mtohost;
+/* Sstc CSRs */
+uint64_t stimecmp;
+
/* physical memory protection */
pmp_table_t pmp_state;
target_ulong mseccfg;
@@ -329,6 +332,7 @@ struct CPUArchState {
float_status fp_status;
/* Fields from here on are preserved across CPU reset. */
+QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
hwaddr kernel_addr;
hwaddr fdt_addr;
@@ -379,6 +383,7 @@ struct RISCVCPUConfig {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+bool ext_sstc;
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4e5b630f5965..29d0e4a1be01 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -215,6 +215,10 @@
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
+/* Sstc supervisor CSRs */
+#define CSR_STIMECMP0x14D
+#define CSR_STIMECMPH 0x15D
+
/* Supervisor Protection and Translation */
#define CSR_SPTBR 0x180
#define CSR_SATP0x180
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 245f007e66e1..48d07911ae14 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -21,6 +21,7 @@
#include "qemu/log.h"
#include "qemu/timer.h"
#include "cpu.h"
+#include "time_helper.h"
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
#include "sysemu/cpu-timers.h"
@@ -537,6 +538,76 @@ static RISCVException read_timeh(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException sstc(CPURISCVState *env, int csrno)
+{
+CPUState *cs = env_cpu(env);
+RISCVCPU *cpu = RISCV_CPU(cs);
+
+if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+if (env->priv == PRV_M) {
+return RISCV_EXCP_NONE;
+}
+
+if (env->priv != PRV_S) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+/*
+ * No need of separate function for rv32 as menvcfg stores both menvcfg
+ * menvcfgh for RV32.
+ */
+if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
+ get_field(env->menvcfg, MENVCFG_STCE))) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
+target_ulong *val)
+{
+*val = env->stimecmp;
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
+
