RE: [PATCH v6 03/12] target/hexagon: make slot number an unsigned

[Taylor Simpson]

> -Original Message-
> From: Alessandro Di Federico 
> Sent: Tuesday, July 20, 2021 7:30 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; bab...@rev.ng; ni...@rev.ng;
> richard.hender...@linaro.org; Alessandro Di Federico 
> Subject: [PATCH v6 03/12] target/hexagon: make slot number an unsigned
> 
> From: Paolo Montesel 
> 
> Signed-off-by: Alessandro Di Federico 
> Signed-off-by: Paolo Montesel 
> Acked-by: Richard Henderson 

Could you describe why this is needed?  I presume it has something to do with 
the type system in the idef-parser?

[PATCH v6 03/12] target/hexagon: make slot number an unsigned

[Alessandro Di Federico via]

From: Paolo Montesel 

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Paolo Montesel 
Acked-by: Richard Henderson 
---
 target/hexagon/macros.h |  2 +-
 target/hexagon/genptr.c | 24 +---
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 094b8dabb5..cd4f878fcf 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -185,7 +185,7 @@
 #define LOAD_CANCEL(EA) do { CANCEL; } while (0)
 
 #ifdef QEMU_GENERATE
-static inline void gen_pred_cancel(TCGv pred, int slot_num)
+static inline void gen_pred_cancel(TCGv pred, uint32_t slot_num)
  {
 TCGv slot_mask = tcg_const_tl(1 << slot_num);
 TCGv tmp = tcg_temp_new();
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 7333299615..2c7f4136b5 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -27,7 +27,8 @@
 #undef QEMU_GENERATE
 #include "gen_tcg.h"
 
-static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
+static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
+uint32_t slot)
 {
 TCGv zero = tcg_const_tl(0);
 TCGv slot_mask = tcg_temp_new();
@@ -60,7 +61,8 @@ static inline void gen_log_reg_write(int rnum, TCGv val)
 }
 }
 
-static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
+static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,
+  uint32_t slot)
 {
 TCGv val32 = tcg_temp_new();
 TCGv zero = tcg_const_tl(0);
@@ -379,7 +381,7 @@ static inline void gen_store_conditional8(DisasContext *ctx,
 tcg_gen_movi_tl(hex_llsc_addr, ~0);
 }
 
-static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot)
+static inline void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
 {
 tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
 tcg_gen_movi_tl(hex_store_width[slot], width);
@@ -387,14 +389,14 @@ static inline void gen_store32(TCGv vaddr, TCGv src, int 
width, int slot)
 }
 
 static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src,
-  DisasContext *ctx, int slot)
+  DisasContext *ctx, uint32_t slot)
 {
 gen_store32(vaddr, src, 1, slot);
 ctx->store_width[slot] = 1;
 }
 
 static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
-   DisasContext *ctx, int slot)
+   DisasContext *ctx, uint32_t slot)
 {
 TCGv tmp = tcg_const_tl(src);
 gen_store1(cpu_env, vaddr, tmp, ctx, slot);
@@ -402,14 +404,14 @@ static inline void gen_store1i(TCGv_env cpu_env, TCGv 
vaddr, int32_t src,
 }
 
 static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
-  DisasContext *ctx, int slot)
+  DisasContext *ctx, uint32_t slot)
 {
 gen_store32(vaddr, src, 2, slot);
 ctx->store_width[slot] = 2;
 }
 
 static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
-   DisasContext *ctx, int slot)
+   DisasContext *ctx, uint32_t slot)
 {
 TCGv tmp = tcg_const_tl(src);
 gen_store2(cpu_env, vaddr, tmp, ctx, slot);
@@ -417,14 +419,14 @@ static inline void gen_store2i(TCGv_env cpu_env, TCGv 
vaddr, int32_t src,
 }
 
 static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src,
-  DisasContext *ctx, int slot)
+  DisasContext *ctx, uint32_t slot)
 {
 gen_store32(vaddr, src, 4, slot);
 ctx->store_width[slot] = 4;
 }
 
 static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
-   DisasContext *ctx, int slot)
+   DisasContext *ctx, uint32_t slot)
 {
 TCGv tmp = tcg_const_tl(src);
 gen_store4(cpu_env, vaddr, tmp, ctx, slot);
@@ -432,7 +434,7 @@ static inline void gen_store4i(TCGv_env cpu_env, TCGv 
vaddr, int32_t src,
 }
 
 static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
-  DisasContext *ctx, int slot)
+  DisasContext *ctx, uint32_t slot)
 {
 tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
 tcg_gen_movi_tl(hex_store_width[slot], 8);
@@ -441,7 +443,7 @@ static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, 
TCGv_i64 src,
 }
 
 static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src,
-   DisasContext *ctx, int slot)
+   DisasContext *ctx, uint32_t slot)
 {
 TCGv_i64 tmp = tcg_const_i64(src);
 gen_store8(cpu_env, vaddr, tmp, ctx, slot);
-- 
2.32.0