Re: [PATCH v6 10/61] target/riscv: vector single-width integer add and subtract

2020-03-28 Thread LIU Zhiwei 




On 2020/3/28 7:54, Richard Henderson wrote:

On 3/17/20 8:06 AM, LIU Zhiwei wrote:

+if (a->vm && s->vl_eq_vlmax) {
+gvec_fn(s->sew, vreg_ofs(s, a->rd),
+vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
+MAXSZ(s), MAXSZ(s));

Indentation is off here.

Do you mean I should adjust the indentation for parameters in gvec_fn like

+if (a->vm && s->vl_eq_vlmax) {
+gvec_fn(s->sew, vreg_ofs(s, a->rd),
+vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
+MAXSZ(s), MAXSZ(s));


+static inline bool
+do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
+  gen_helper_opivx *fn)
+{
+if (!opivx_check(s, a)) {
+return false;
+}
+
+if (a->vm && s->vl_eq_vlmax) {
+TCGv_i64 src1 = tcg_temp_new_i64();
+TCGv tmp = tcg_temp_new();
+
+gen_get_gpr(tmp, a->rs1);
+tcg_gen_ext_tl_i64(src1, tmp);
+gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
+src1, MAXSZ(s), MAXSZ(s));
+
+tcg_temp_free_i64(src1);
+tcg_temp_free(tmp);
+return true;
+} else {
+return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+}
+return true;
+}

This final return is unreachable, and I'm sure some static analyzer (e.g.
Coverity) will complain.

Since the if-then has a return, we can drop the else like so:

 if (a->vm && s->vl_eq_vlmax) {
 ...
 return true;
 }
 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);

Yes, it's tidier. Thanks.

Zhiwei


Otherwise,
Reviewed-by: Richard Henderson 

r~

Re: [PATCH v6 10/61] target/riscv: vector single-width integer add and subtract

2020-03-27 Thread Richard Henderson 
On 3/17/20 8:06 AM, LIU Zhiwei wrote:
> +if (a->vm && s->vl_eq_vlmax) {
> +gvec_fn(s->sew, vreg_ofs(s, a->rd),
> +vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
> +MAXSZ(s), MAXSZ(s));

Indentation is off here.

> +static inline bool
> +do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
> +  gen_helper_opivx *fn)
> +{
> +if (!opivx_check(s, a)) {
> +return false;
> +}
> +
> +if (a->vm && s->vl_eq_vlmax) {
> +TCGv_i64 src1 = tcg_temp_new_i64();
> +TCGv tmp = tcg_temp_new();
> +
> +gen_get_gpr(tmp, a->rs1);
> +tcg_gen_ext_tl_i64(src1, tmp);
> +gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
> +src1, MAXSZ(s), MAXSZ(s));
> +
> +tcg_temp_free_i64(src1);
> +tcg_temp_free(tmp);
> +return true;
> +} else {
> +return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
> +}
> +return true;
> +}

This final return is unreachable, and I'm sure some static analyzer (e.g.
Coverity) will complain.

Since the if-then has a return, we can drop the else like so:

if (a->vm && s->vl_eq_vlmax) {
...
return true;
}
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);

Otherwise,
Reviewed-by: Richard Henderson 

r~

Re: [PATCH v6 10/61] target/riscv: vector single-width integer add and subtract

2020-03-20 Thread Alistair Francis 
On Tue, Mar 17, 2020 at 8:27 AM LIU Zhiwei  wrote:
>
> Signed-off-by: LIU Zhiwei 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/helper.h   |  21 ++
>  target/riscv/insn32.decode  |  10 +
>  target/riscv/insn_trans/trans_rvv.inc.c | 251 
>  target/riscv/vector_helper.c| 149 ++
>  4 files changed, 431 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 70a4b05f75..e73701d4bb 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -269,3 +269,24 @@ DEF_HELPER_6(vamominw_v_w,  void, ptr, ptr, tl, ptr, 
> env, i32)
>  DEF_HELPER_6(vamomaxw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
> +
> +DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vsub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vsub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vsub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vsub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vsub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vrsub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vrsub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vrsub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vrsub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 1330703720..d1034a0e61 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -44,6 +44,7 @@
>  imm rd
>   shamt rs1 rd
>  aq rl rs2 rs1 rd
> +  vm rd rs1 rs2
>   vm wd rd rs1 rs2
>  vm rd rs1 nf
>   vm rd rs1 rs2 nf
> @@ -68,6 +69,7 @@
>  @r2  ...   . . ... . ... %rs1 %rd
>  @r2_nfvm ... ... vm:1 . . ... . ...  %nf %rs1 %rd
>  @r_nfvm  ... ... vm:1 . . ... . ...  %nf %rs2 %rs1 %rd
> +@r_vm.. vm:1 . . ... . ...  %rs2 %rs1 %rd
>  @r_wdvm  . wd:1 vm:1 . . ... . ...  %rs2 %rs1 %rd
>  @r2_zimm . zimm:11  . ... . ... %rs1 %rd
>
> @@ -275,5 +277,13 @@ vamominuw_v 11000 . . . . 110 . 010 
> @r_wdvm
>  vamomaxuw_v 11100 . . . . 110 . 010 @r_wdvm
>
>  # *** new major opcode OP-V ***
> +vadd_vv 00 . . . 000 . 1010111 @r_vm
> +vadd_vx 00 . . . 100 . 1010111 @r_vm
> +vadd_vi 00 . . . 011 . 1010111 @r_vm
> +vsub_vv 10 . . . 000 . 1010111 @r_vm
> +vsub_vx 10 . . . 100 . 1010111 @r_vm
> +vrsub_vx11 . . . 100 . 1010111 @r_vm
> +vrsub_vi11 . . . 011 . 1010111 @r_vm
> +
>  vsetvli 0 ... . 111 . 1010111  @r2_zimm
>  vsetvl  100 . . 111 . 1010111  @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
> b/target/riscv/insn_trans/trans_rvv.inc.c
> index a8722ed9d2..c68f6ffe3b 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -740,3 +740,254 @@ GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
>  GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
>  GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
>  #endif
> +
> +/*
> + *** Vector Integer Arithmetic Instructions
> + */
> +#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
> +
> +static bool opivv_check(DisasContext *s, arg_rmrr *a)
> +{
> +return (vext_check_isa_ill(s) &&
> +vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> +vext_check_reg(s, a->rd, false) &&
> +vext_check_reg(s, a->rs2, false) &&
> +vext_check_reg(s, a->rs1, false));
> +}
> +
> +typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
> +uint32_t, uint32_t, uint32_t);
> +
> +static inline bool
> +do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
> +  gen_helper_gvec_4_ptr *fn)
> +{
> +if (!opivv_check(s, a)) {
> +return false;
> +}
> +
> +if (a->vm && s->vl_eq_vlmax) {
> +gvec_fn(s->sew, vreg_ofs(s, a->rd),
> +vreg_ofs(s,

[PATCH v6 10/61] target/riscv: vector single-width integer add and subtract

2020-03-17 Thread LIU Zhiwei 
Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |  21 ++
 target/riscv/insn32.decode  |  10 +
 target/riscv/insn_trans/trans_rvv.inc.c | 251 
 target/riscv/vector_helper.c| 149 ++
 4 files changed, 431 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 70a4b05f75..e73701d4bb 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -269,3 +269,24 @@ DEF_HELPER_6(vamominw_v_w,  void, ptr, ptr, tl, ptr, env, 
i32)
 DEF_HELPER_6(vamomaxw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrsub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrsub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrsub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrsub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1330703720..d1034a0e61 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -44,6 +44,7 @@
 imm rd
  shamt rs1 rd
 aq rl rs2 rs1 rd
+  vm rd rs1 rs2
  vm wd rd rs1 rs2
 vm rd rs1 nf
  vm rd rs1 rs2 nf
@@ -68,6 +69,7 @@
 @r2  ...   . . ... . ... %rs1 %rd
 @r2_nfvm ... ... vm:1 . . ... . ...  %nf %rs1 %rd
 @r_nfvm  ... ... vm:1 . . ... . ...  %nf %rs2 %rs1 %rd
+@r_vm.. vm:1 . . ... . ...  %rs2 %rs1 %rd
 @r_wdvm  . wd:1 vm:1 . . ... . ...  %rs2 %rs1 %rd
 @r2_zimm . zimm:11  . ... . ... %rs1 %rd
 
@@ -275,5 +277,13 @@ vamominuw_v 11000 . . . . 110 . 010 
@r_wdvm
 vamomaxuw_v 11100 . . . . 110 . 010 @r_wdvm
 
 # *** new major opcode OP-V ***
+vadd_vv 00 . . . 000 . 1010111 @r_vm
+vadd_vx 00 . . . 100 . 1010111 @r_vm
+vadd_vi 00 . . . 011 . 1010111 @r_vm
+vsub_vv 10 . . . 000 . 1010111 @r_vm
+vsub_vx 10 . . . 100 . 1010111 @r_vm
+vrsub_vx11 . . . 100 . 1010111 @r_vm
+vrsub_vi11 . . . 011 . 1010111 @r_vm
+
 vsetvli 0 ... . 111 . 1010111  @r2_zimm
 vsetvl  100 . . 111 . 1010111  @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index a8722ed9d2..c68f6ffe3b 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -740,3 +740,254 @@ GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
 #endif
+
+/*
+ *** Vector Integer Arithmetic Instructions
+ */
+#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
+
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs2, false) &&
+vext_check_reg(s, a->rs1, false));
+}
+
+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
+uint32_t, uint32_t, uint32_t);
+
+static inline bool
+do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
+  gen_helper_gvec_4_ptr *fn)
+{
+if (!opivv_check(s, a)) {
+return false;
+}
+
+if (a->vm && s->vl_eq_vlmax) {
+gvec_fn(s->sew, vreg_ofs(s, a->rd),
+vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
+MAXSZ(s), MAXSZ(s));
+} else {
+uint32_t data = 0;
+
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+data = FIELD_DP32(data, VDATA, VM, a->vm);
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+tcg_gen_gvec_4_ptr(vreg_ofs(s,