This should be fully reviewed now, but the Timer patch may deserve another
look, as I fixed a few bugs in it. Huge thanks to everyone who reviewed and/or
tested this patchset, it has clearly improved a lot since I started.
I also pushed this and the previous patchsets to my qemu fork on github. The
branches are named npcm7xx-v[1-9].
https://github.com/hskinnemoen/qemu
This patch series models enough of the Nuvoton NPCM730 and NPCM750 SoCs to boot
an OpenBMC image built for quanta-gsj. This includes device models for:
- Global Configuration Registers
- Clock Control
- Timers
- Fuses
- Memory Controller
- Flash Controller
These modules, along with the existing Cortex A9 CPU cores and built-in
peripherals, are integrated into a NPCM730 or NPCM750 SoC, which in turn form
the foundation for the quanta-gsj and npcm750-evb machines, respectively. The
two SoCs are very similar; the only difference is that NPCM730 is missing some
peripherals that NPCM750 has, and which are not considered essential for
datacenter use (e.g. graphics controllers). For more information, see
https://www.nuvoton.com/products/cloud-computing/ibmc/
Both quanta-gsj and npcm750-evb correspond to real boards supported by OpenBMC.
At the end of the series, qemu can boot an OpenBMC image built for one of these
boards with some minor modifications.
The patches in this series were developed by Google and reviewed by Nuvoton. We
will be maintaining the machine and peripheral support together.
The data sheet for these SoCs is not generally available. Please let me know if
more comments are needed to understand the device behavior.
Changes since v8:
- Add missing class_size initializer for TYPE_NPCM7XX_OTP.
- Timer bug fixes:
- Interrupt Enable bit should not be reserved.
- Update expiration time and/or time remaining on prescaler changes.
- Warn when CEN and CRST are both set, and force CEN to zero.
- Fix crash when the timer is loaded with zero cycles, and CEN is set and
cleared in the same cycle (found by Alexander Bulekov's fuzz testing).
- Update CACT when CEN changes.
- De-assert interrupts when TISR bits are cleared by guest writes.
- Load the bootrom for direct kernel boot if it's available, but don't error
out if it's not.
- Add the usual openbmc password to the arm/nuvoton docs.
Changes since v7:
- Move register enums to .c files throughout, leaving a single
NPCM7XX_FOO_NR_REGS definition behind in the .h file. A QEMU_BUILD_BUG_ON
should alert anyone accidentally expanding the register enum that they need
to update the corresponding NR_REGS define, which in turn has a comment
reminding them to update the vmstate version_id as well.
- Skip loading the bootrom if a kernel filename is provided by the user.
- New patch adding a board setup stub to tweak clocks before booting directly
into the kernel.
- Add stuff to meson files instead of Makefiles.
- Try to disable the slowest drivers and services to speed up the flash boot
acceptance test a bit. This is somewhat based on the following
systemd-analyze blame report:
https://gist.github.com/hskinnemoen/475cb0676530cd2cebaa1754cf16ca97
Changes since v6:
- Use size_to_str to report DRAM sizes in npcm7xx_gcr.
- Simplify the interrupt logic in npcm7xx_timer.
- Update global bios_name instead of temporary.
- Add npcm7xx_bootrom to MAINTAINERS and pc-bios/README.
- Use a predefined name for the gsj boot image in the acceptance test.
Changes since v5:
- Boot ROM included, as a git submodule and a binary blob, and loaded by
default, so the -bios option is usually not necessary anymore.
- Two acceptance tests added (openbmc image boot, and direct kernel boot).
- npcm7xx_load_kernel() moved to SoC code.
- NPCM7XX_TIMER_REF_HZ definition moved to CLK header.
- Comments added clarifying available SPI flash chip selects.
- Error handling adjustments:
- Errors from CPU and GCR realization are propagated through the SoC
since they may be triggered by user-configurable parameters.
- Machine init uses error_fatal instead of error_abort for SoC
realization flash init. This makes error messages more helpful.
- Comments added to indicate whether peripherals may fail to realize.
- Use ERRP_GUARD() instead of Error *err when possible.
- Default CPU type is now set, and attempting to set it to anything else
will fail.
- Format string fixes (use HWADDR_PRIx, etc.)
- Simplified memory size encoding and error checking in npcm7xx_gcr.
- Encapsulate non-obvious pointer subtraction into helper functions in the
FIU and TIMER modules.
- Incorporate review feedback into the FIU module:
- Add select/deselect trace events.
- Use npcm7xx_fiu_{de,}select() consistently.
- Use extract/deposit in more places for consistency.
- Use -Wimplicit-fallthrough compatible fallthrough comments.
- Use qdev_init_gpio_
