Re: [PULL 00/29] target-arm queue
On 7/1/24 09:07, Peter Maydell wrote: The following changes since commit b6d32a06fc0984e537091cba08f2e1ed9f775d74: Merge tag 'pull-trivial-patches' ofhttps://gitlab.com/mjt0k/qemu into staging (2024-06-30 16:12:24 -0700) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240701 for you to fetch changes up to 58c782de557beb496bfb4c5ade721bbbd2480c72: tests/qtest: Ensure STM32L4x5 EXTI state is correct at the end of QTests (2024-07-01 15:40:54 +0100) target-arm queue: * tests/avocado: update firmware for sbsa-ref and use all cores * hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev * arm: Fix VCMLA Dd, Dn, Dm[idx] * arm: Fix SQDMULH (by element) with Q=0 * arm: Fix FJCVTZS vs flush-to-zero * arm: More conversion of A64 AdvSIMD to decodetree * arm: Enable FEAT_Debugv8p8 for -cpu max * MAINTAINERS: Update family name for Patrick Leis * hw/arm/xilinx_zynq: Add boot-mode property * docs/system/arm: Add a doc for zynq board * hw/misc: In STM32L4x5 EXTI, correct configurable interrupts * tests/qtest: fix minor issues in STM32L4x5 tests Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~
[PULL 00/29] target-arm queue
The following changes since commit b6d32a06fc0984e537091cba08f2e1ed9f775d74: Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2024-06-30 16:12:24 -0700) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240701 for you to fetch changes up to 58c782de557beb496bfb4c5ade721bbbd2480c72: tests/qtest: Ensure STM32L4x5 EXTI state is correct at the end of QTests (2024-07-01 15:40:54 +0100) target-arm queue: * tests/avocado: update firmware for sbsa-ref and use all cores * hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev * arm: Fix VCMLA Dd, Dn, Dm[idx] * arm: Fix SQDMULH (by element) with Q=0 * arm: Fix FJCVTZS vs flush-to-zero * arm: More conversion of A64 AdvSIMD to decodetree * arm: Enable FEAT_Debugv8p8 for -cpu max * MAINTAINERS: Update family name for Patrick Leis * hw/arm/xilinx_zynq: Add boot-mode property * docs/system/arm: Add a doc for zynq board * hw/misc: In STM32L4x5 EXTI, correct configurable interrupts * tests/qtest: fix minor issues in STM32L4x5 tests Gustavo Romero (3): target/arm: Fix indentation target/arm: Move initialization of debug ID registers target/arm: Enable FEAT_Debugv8p8 for -cpu max Inès Varhol (3): tests/qtest: Fix STM32L4x5 SYSCFG irq line 15 state assumption hw/misc: In STM32L4x5 EXTI, correct configurable interrupts tests/qtest: Ensure STM32L4x5 EXTI state is correct at the end of QTests Marcin Juszkiewicz (2): tests/avocado: update firmware for sbsa-ref tests/avocado: use default amount of cores on sbsa-ref Nicolin Chen (1): hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev Patrick Leis (1): MAINTAINERS: Update my family name Rayhan Faizel (3): hw/nvram: Add BCM2835 OTP device hw/arm: Connect OTP device to BCM2835 hw/misc: Implement mailbox properties for customer OTP and device specific private keys Richard Henderson (13): target/arm: Fix VCMLA Dd, Dn, Dm[idx] target/arm: Fix SQDMULH (by element) with Q=0 target/arm: Fix FJCVTZS vs flush-to-zero target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree target/arm: Convert SDOT, UDOT to decodetree target/arm: Convert SUDOT, USDOT to decodetree target/arm: Convert BFDOT to decodetree target/arm: Convert BFMLALB, BFMLALT to decodetree target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree target/arm: Add data argument to do_fp3_vector target/arm: Convert FCADD to decodetree target/arm: Convert FCMLA to decodetree target/arm: Delete dead code from disas_simd_indexed Sai Pavan Boddu (3): hw/misc/zynq_slcr: Add boot-mode property hw/arm/xilinx_zynq: Add boot-mode property docs/system/arm: Add a doc for zynq board MAINTAINERS | 3 +- docs/system/arm/emulation.rst| 1 + docs/system/arm/xlnx-zynq.rst| 47 ++ docs/system/target-arm.rst | 1 + include/hw/arm/bcm2835_peripherals.h | 3 +- include/hw/arm/raspberrypi-fw-defs.h | 2 + include/hw/arm/smmu-common.h | 4 +- include/hw/misc/bcm2835_property.h | 2 + include/hw/misc/stm32l4x5_exti.h | 2 + include/hw/nvram/bcm2835_otp.h | 68 +++ target/arm/cpu.h | 2 + target/arm/helper.h | 10 + target/arm/tcg/a64.decode| 43 ++ hw/arm/bcm2835_peripherals.c | 15 +- hw/arm/smmu-common.c | 8 +- hw/arm/smmuv3.c | 12 +- hw/arm/xilinx_zynq.c | 31 ++ hw/misc/bcm2835_property.c | 87 hw/misc/stm32l4x5_exti.c | 28 +- hw/misc/zynq_slcr.c | 22 +- hw/nvram/bcm2835_otp.c | 187 +++ target/arm/tcg/cpu32.c | 35 +- target/arm/tcg/cpu64.c | 4 +- target/arm/tcg/translate-a64.c | 808 ++- target/arm/tcg/vec_helper.c | 100 +++- target/arm/vfp_helper.c | 18 +- tests/qtest/stm32l4x5_exti-test.c| 8 + tests/qtest/stm32l4x5_syscfg-test.c | 16 +- tests/tcg/aarch64/test-2375.c| 21 + hw/nvram/meson.build | 1 + tests/avocado/machine_aarch64_sbsaref.py | 16 +- tests/tcg/aarch64/Makefile.target| 3 +- 32 files changed, 967 insertions(+), 641 deletions(-) create mode 100644 docs/system/arm/xlnx-zynq.rst create mode 100644 include/hw/nvram/bcm2835_otp.h create mode 100644 hw/nvram/bcm2835_otp.c create mode 100644 tests/tcg/aarch64/test-2375.c
Re: [PULL 00/29] target-arm queue
On 5/18/23 05:50, Peter Maydell wrote: Hi; this mostly contains the first slice of A64 decodetree patches, plus some other minor pieces. It also has the enablement of MTE for KVM guests. thanks -- PMM The following changes since commit d27e7c359330ba7020bdbed7ed2316cb4cf6ffc1: qapi/parser: Drop two bad type hints for now (2023-05-17 10:18:33 -0700) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230518 for you to fetch changes up to 91608e2a44f36e79cb83f863b8a7bb57d2c98061: docs: Convert u2f.txt to rST (2023-05-18 11:40:32 +0100) target-arm queue: * Fix vd == vm overlap in sve_ldff1_z * Add support for MTE with KVM guests * Add RAZ/WI handling for DBGDTR[TX|RX] * Start of conversion of A64 decoder to decodetree * Saturate L2CTLR_EL1 core count field rather than overflowing * vexpress: Avoid trivial memory leak of 'flashalias' * sbsa-ref: switch default cpu core to Neoverse-N1 * sbsa-ref: use Bochs graphics card instead of VGA * MAINTAINERS: Add Marcin Juszkiewicz to sbsa-ref reviewer list * docs: Convert u2f.txt to rST Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate. r~
[PULL 00/29] target-arm queue
Hi; this mostly contains the first slice of A64 decodetree patches, plus some other minor pieces. It also has the enablement of MTE for KVM guests. thanks -- PMM The following changes since commit d27e7c359330ba7020bdbed7ed2316cb4cf6ffc1: qapi/parser: Drop two bad type hints for now (2023-05-17 10:18:33 -0700) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230518 for you to fetch changes up to 91608e2a44f36e79cb83f863b8a7bb57d2c98061: docs: Convert u2f.txt to rST (2023-05-18 11:40:32 +0100) target-arm queue: * Fix vd == vm overlap in sve_ldff1_z * Add support for MTE with KVM guests * Add RAZ/WI handling for DBGDTR[TX|RX] * Start of conversion of A64 decoder to decodetree * Saturate L2CTLR_EL1 core count field rather than overflowing * vexpress: Avoid trivial memory leak of 'flashalias' * sbsa-ref: switch default cpu core to Neoverse-N1 * sbsa-ref: use Bochs graphics card instead of VGA * MAINTAINERS: Add Marcin Juszkiewicz to sbsa-ref reviewer list * docs: Convert u2f.txt to rST Alex Bennée (1): target/arm: add RAZ/WI handling for DBGDTR[TX|RX] Cornelia Huck (1): arm/kvm: add support for MTE Marcin Juszkiewicz (3): sbsa-ref: switch default cpu core to Neoverse-N1 Maintainers: add myself as reviewer for sbsa-ref sbsa-ref: use Bochs graphics card instead of VGA Peter Maydell (14): target/arm: Create decodetree skeleton for A64 target/arm: Pull calls to disas_sve() and disas_sme() out of legacy decoder target/arm: Convert Extract instructions to decodetree target/arm: Convert unconditional branch immediate to decodetree target/arm: Convert CBZ, CBNZ to decodetree target/arm: Convert TBZ, TBNZ to decodetree target/arm: Convert conditional branch insns to decodetree target/arm: Convert BR, BLR, RET to decodetree target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree target/arm: Convert ERET, ERETAA, ERETAB to decodetree target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing hw/arm/vexpress: Avoid trivial memory leak of 'flashalias' docs: Convert u2f.txt to rST Richard Henderson (10): target/arm: Fix vd == vm overlap in sve_ldff1_z target/arm: Split out disas_a64_legacy target/arm: Convert PC-rel addressing to decodetree target/arm: Split gen_add_CC and gen_sub_CC target/arm: Convert Add/subtract (immediate) to decodetree target/arm: Convert Add/subtract (immediate with tags) to decodetree target/arm: Replace bitmask64 with MAKE_64BIT_MASK target/arm: Convert Logical (immediate) to decodetree target/arm: Convert Move wide (immediate) to decodetree target/arm: Convert Bitfield to decodetree MAINTAINERS |1 + docs/system/device-emulation.rst |1 + docs/system/devices/usb-u2f.rst | 93 +++ docs/system/devices/usb.rst |2 +- docs/u2f.txt | 110 target/arm/cpu.h |4 + target/arm/kvm_arm.h | 19 + target/arm/tcg/translate.h |5 + target/arm/tcg/a64.decode| 152 + hw/arm/sbsa-ref.c|4 +- hw/arm/vexpress.c| 40 +- hw/arm/virt.c| 73 ++- target/arm/cortex-regs.c | 11 +- target/arm/cpu.c |9 +- target/arm/debug_helper.c| 11 +- target/arm/kvm.c | 35 + target/arm/kvm64.c |5 + target/arm/tcg/sve_helper.c |6 + target/arm/tcg/translate-a64.c | 1321 -- target/arm/tcg/meson.build |1 + 20 files changed, 979 insertions(+), 924 deletions(-) create mode 100644 docs/system/devices/usb-u2f.rst delete mode 100644 docs/u2f.txt create mode 100644 target/arm/tcg/a64.decode
[PULL 00/29] target-arm queue
First arm pullreq of the 8.0 series... The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873: Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215 for you to fetch changes up to 4f3ebdc33618e7c163f769047859d6f34373e3af: target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 11:18:20 +) target-arm queue: * hw/arm/virt: Add properties to allow more granular configuration of use of highmem space * target/arm: Add Cortex-A55 CPU * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement * Implement FEAT_EVT * Some 3-phase-reset conversions for Arm GIC, SMMU * hw/arm/boot: set initrd with #address-cells type in fdt * align user-mode exposed ID registers with Linux * hw/misc: Move some arm-related files from specific_ss into softmmu_ss * Restrict arm_cpu_exec_interrupt() to TCG accelerator Gavin Shan (7): hw/arm/virt: Introduce virt_set_high_memmap() helper hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap() hw/arm/virt: Introduce variable region_base in virt_set_high_memmap() hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper hw/arm/virt: Improve high memory region address assignment hw/arm/virt: Add 'compact-highmem' property hw/arm/virt: Add properties to disable high memory regions Luke Starrett (1): hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement Mihai Carabas (1): hw/arm/virt: build SMBIOS 19 table Peter Maydell (15): target/arm: Allow relevant HCR bits to be written for FEAT_EVT target/arm: Implement HCR_EL2.TTLBIS traps target/arm: Implement HCR_EL2.TTLBOS traps target/arm: Implement HCR_EL2.TICAB,TOCU traps target/arm: Implement HCR_EL2.TID4 traps target/arm: Report FEAT_EVT for TCG '-cpu max' hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset Philippe Mathieu-Daudé (1): target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator Schspa Shi (1): hw/arm/boot: set initrd with #address-cells type in fdt Thomas Huth (1): hw/misc: Move some arm-related files from specific_ss into softmmu_ss Timofey Kutergin (1): target/arm: Add Cortex-A55 CPU Zhuojia Shen (1): target/arm: align exposed ID registers with Linux docs/system/arm/emulation.rst | 1 + docs/system/arm/virt.rst | 18 +++ include/hw/arm/smmuv3.h| 2 +- include/hw/arm/virt.h | 2 + include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +- target/arm/cpu.h | 30 + target/arm/kvm-consts.h| 8 +- hw/arm/boot.c | 10 +- hw/arm/smmu-common.c | 7 +- hw/arm/smmuv3.c| 12 +- hw/arm/virt.c | 202 +++- hw/intc/arm_gic_common.c | 7 +- hw/intc/arm_gic_kvm.c | 14 +- hw/intc/arm_gicv3_common.c | 7 +- hw/intc/arm_gicv3_dist.c | 4 +- hw/intc/arm_gicv3_its.c| 14 +- hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c| 14 +- hw/intc/arm_gicv3_kvm.c| 14 +- hw/misc/imx6_src.c | 2 +- hw/misc/iotkit-sysctl.c| 1 - target/arm/cpu.c | 5 +- target/arm/cpu64.c | 70 ++ target/arm/cpu_tcg.c | 1 + target/arm/helper.c| 231 - hw/misc/meson.build| 11 +- 26 files changed, 538 insertions(+), 158 deletions(-)
Re: [PULL 00/29] target-arm queue
On Fri, 5 Jun 2020 at 17:50, Peter Maydell wrote: > > Arm queue; some of the simpler stuff, things other have reviewed (thanks!), > etc. > > -- PMM > > The following changes since commit 5d2f557b47dfbf8f23277a5bdd8473d4607c681a: > > Merge remote-tracking branch > 'remotes/kraxel/tags/vga-20200605-pull-request' into staging (2020-06-05 > 13:53:05 +0100) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20200605 > > for you to fetch changes up to 2c35a39eda0b16c2ed85c94cec204bf5efb97812: > > target/arm: Convert Neon one-register-and-immediate insns to decodetree > (2020-06-05 17:23:10 +0100) > > > target-arm queue: > hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly > hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask() > hw/arm/pxa2xx: Replace printf() call by qemu_log_mask() > target/arm: Convert crypto insns to gvec > hw/adc/stm32f2xx_adc: Correct memory region size and access size > tests/acceptance: Add a boot test for the xlnx-versal-virt machine > docs/system: Document Aspeed boards > raspi: Add model of the USB controller > target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1 for any user-visible changes. -- PMM
Re: [PULL 00/29] target-arm queue
Patchew URL: https://patchew.org/QEMU/20200605165007.12095-1-peter.mayd...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 20200605165007.12095-1-peter.mayd...@linaro.org Subject: [PULL 00/29] target-arm queue Type: series === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu 5d2f557..175198a master -> master Switched to a new branch 'test' 8d19bb1 target/arm: Convert Neon one-register-and-immediate insns to decodetree c07ebcb target/arm: Convert VCVT fixed-point ops to decodetree 595e77e target/arm: Convert Neon VSHLL, VMOVL to decodetree 0f42979 target/arm: Convert Neon narrowing shifts with op==9 to decodetree 93549e8 target/arm: Convert Neon narrowing shifts with op==8 to decodetree f0efe71 target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree c0457fa target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree 7e946c5 target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree 3daf164 target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree 725f9e4 raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host 2a56c0c wire in the dwc-hsotg (dwc2) USB host controller emulation f9720e8 usb: add short-packet handling to usb-storage driver d6df0bc dwc-hsotg (dwc2) USB host controller emulation 26ec413 dwc-hsotg (dwc2) USB host controller state definitions 27c3b07 dwc-hsotg (dwc2) USB host controller register definitions 3f982e5 raspi: add BCM2835 SOC MPHI emulation 21a59c9 docs/system: Document Aspeed boards 65b3e83 tests/acceptance: Add a boot test for the xlnx-versal-virt machine a494cb0 hw/adc/stm32f2xx_adc: Correct memory region size and access size abbdeb5 target/arm: Split helper_crypto_sm3tt 0db4fd4 target/arm: Split helper_crypto_sha1_3reg 00ad42c target/arm: Convert sha1 and sha256 to gvec helpers 96fc084 target/arm: Convert sha512 and sm3 to gvec helpers 5199605 target/arm: Convert rax1 to gvec helpers 7cd9082 target/arm: Convert aes and sm4 to gvec helpers 188335a hw/arm/pxa2xx: Replace printf() call by qemu_log_mask() 240dce6 hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask() b09557e hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave f979463 hw/ssi/imx_spi: changed while statement to prevent underflow === OUTPUT BEGIN === 1/29 Checking commit f979463e1fdd (hw/ssi/imx_spi: changed while statement to prevent underflow) 2/29 Checking commit b09557efe185 (hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave) 3/29 Checking commit 240dce66be50 (hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()) 4/29 Checking commit 188335aa83c3 (hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()) 5/29 Checking commit 7cd9082434bd (target/arm: Convert aes and sm4 to gvec helpers) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #396: new file mode 100644 total: 0 errors, 1 warnings, 364 lines checked Patch 5/29 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 6/29 Checking commit 519960531b00 (target/arm: Convert rax1 to gvec helpers) 7/29 Checking commit 96fc08401629 (target/arm: Convert sha512 and sm3 to gvec helpers) 8/29 Checking commit 00ad42c753c1 (target/arm: Convert sha1 and sha256 to gvec helpers) ERROR: spaces required around that '*' (ctx:WxV) #270: FILE: target/arm/translate-neon.inc.c:735: +static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a)\ ^ total: 1 errors, 0 warnings, 366 lines checked Patch 8/29 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 9/29 Checking commit 0db4fd4a19b7 (target/arm: Split helper_crypto_sha1_3reg) ERROR: spaces required around that '*' (ctx:WxV) #246: FILE: target/arm/translate-neon.inc.c:698: +static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a)\ ^ total: 1 errors, 0 warnings, 243 lines checked Patch 9/29 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 10/29 Checking commit abbdeb5eb100 (target/arm: Split helper_crypto_sm3tt) 11/29 Checking commit a494cb00d665 (hw/adc/stm32f2xx_adc: Correct memory region size and access size) 12/29 Checking commit 65b3e832526b (tests/acceptance: Add a boot test for the xlnx-versal-virt machine) 13/29 Checking commit 21a59c
[PULL 00/29] target-arm queue
Arm queue; some of the simpler stuff, things other have reviewed (thanks!), etc. -- PMM The following changes since commit 5d2f557b47dfbf8f23277a5bdd8473d4607c681a: Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200605-pull-request' into staging (2020-06-05 13:53:05 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200605 for you to fetch changes up to 2c35a39eda0b16c2ed85c94cec204bf5efb97812: target/arm: Convert Neon one-register-and-immediate insns to decodetree (2020-06-05 17:23:10 +0100) target-arm queue: hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask() hw/arm/pxa2xx: Replace printf() call by qemu_log_mask() target/arm: Convert crypto insns to gvec hw/adc/stm32f2xx_adc: Correct memory region size and access size tests/acceptance: Add a boot test for the xlnx-versal-virt machine docs/system: Document Aspeed boards raspi: Add model of the USB controller target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree Cédric Le Goater (1): docs/system: Document Aspeed boards Eden Mikitas (2): hw/ssi/imx_spi: changed while statement to prevent underflow hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave Paul Zimmerman (7): raspi: add BCM2835 SOC MPHI emulation dwc-hsotg (dwc2) USB host controller register definitions dwc-hsotg (dwc2) USB host controller state definitions dwc-hsotg (dwc2) USB host controller emulation usb: add short-packet handling to usb-storage driver wire in the dwc-hsotg (dwc2) USB host controller emulation raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host Peter Maydell (9): target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree target/arm: Convert Neon narrowing shifts with op==8 to decodetree target/arm: Convert Neon narrowing shifts with op==9 to decodetree target/arm: Convert Neon VSHLL, VMOVL to decodetree target/arm: Convert VCVT fixed-point ops to decodetree target/arm: Convert Neon one-register-and-immediate insns to decodetree Philippe Mathieu-Daudé (3): hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask() hw/arm/pxa2xx: Replace printf() call by qemu_log_mask() hw/adc/stm32f2xx_adc: Correct memory region size and access size Richard Henderson (6): target/arm: Convert aes and sm4 to gvec helpers target/arm: Convert rax1 to gvec helpers target/arm: Convert sha512 and sm3 to gvec helpers target/arm: Convert sha1 and sha256 to gvec helpers target/arm: Split helper_crypto_sha1_3reg target/arm: Split helper_crypto_sm3tt Thomas Huth (1): tests/acceptance: Add a boot test for the xlnx-versal-virt machine docs/system/arm/aspeed.rst | 85 ++ docs/system/target-arm.rst |1 + hw/usb/hcd-dwc2.h | 190 + include/hw/arm/bcm2835_peripherals.h |5 +- include/hw/misc/bcm2835_mphi.h | 44 + include/hw/usb/dwc2-regs.h | 899 target/arm/helper.h| 45 +- target/arm/translate-a64.h |3 + target/arm/vec_internal.h | 33 + target/arm/neon-dp.decode | 214 - hw/adc/stm32f2xx_adc.c |4 +- hw/arm/bcm2835_peripherals.c | 38 +- hw/arm/pxa2xx.c| 66 +- hw/input/pxa2xx_keypad.c | 10 +- hw/misc/bcm2835_mphi.c | 191 + hw/ssi/imx_spi.c |4 +- hw/usb/dev-storage.c | 15 +- hw/usb/hcd-dwc2.c | 1417 target/arm/crypto_helper.c | 267 -- target/arm/translate-a64.c | 198 ++--- target/arm/translate-neon.inc.c| 796 ++ target/arm/translate.c | 539 +--- target/arm/vec_helper.c| 12 +- hw/misc/Makefile.objs |1 + hw/usb/Kconfig |5 + hw/usb/Makefile.objs |1 + hw/usb/trace-events| 50 ++ tests/acceptance/boot_linux_console.py | 35 +- 28 files changed, 4258 insertions(+), 910 deletions(-) create mode 100644 docs/system/arm/aspeed.rst create mode 100644 hw/usb/hcd-dwc2.h create mode 100644 include/hw/misc/bcm2835_mphi.h create mode 100644 include/hw/usb/dwc2-regs.h create mode 100644 target/arm/vec
[PULL 00/29] target-arm queue
target-arm queue: nothing big, just a collection of minor things. -- PMM The following changes since commit ae3aa5da96f4ccf0c2a28851449d92db9fcfad71: Merge remote-tracking branch 'remotes/berrange/tags/socket-next-pull-request' into staging (2020-05-21 16:47:28 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200521 for you to fetch changes up to 17b5df7b65d0192c5d775b5e1581518580774c77: linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 (2020-05-21 20:00:19 +0100) target-arm queue: * tests/acceptance: Add a test for the canon-a1100 machine * docs/system: Document some of the Arm development boards * linux-user: make BKPT insn cause SIGTRAP, not be a syscall * target/arm: Remove unused GEN_NEON_INTEGER_OP macro * fsl-imx25, fsl-imx31, fsl-imx6, fsl-imx6ul, fsl-imx7: implement watchdog * hw/arm: Use qemu_log_mask() instead of hw_error() in various places * ARM: PL061: Introduce N_GPIOS * target/arm: Improve clear_vec_high() usage * target/arm: Allow user-mode code to write CPSR.E via MSR * linux-user/arm: Reset CPSR_E when entering a signal handler * linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 Amanieu d'Antras (1): linux-user/arm: Reset CPSR_E when entering a signal handler Geert Uytterhoeven (1): ARM: PL061: Introduce N_GPIOS Guenter Roeck (8): hw: Move i.MX watchdog driver to hw/watchdog hw/watchdog: Implement full i.MX watchdog support hw/arm/fsl-imx25: Wire up watchdog hw/arm/fsl-imx31: Wire up watchdog hw/arm/fsl-imx6: Connect watchdog interrupts hw/arm/fsl-imx6ul: Connect watchdog interrupts hw/arm/fsl-imx7: Instantiate various unimplemented devices hw/arm/fsl-imx7: Connect watchdog interrupts Peter Maydell (12): docs/system: Add 'Arm' to the Integrator/CP document title docs/system: Sort Arm board index into alphabetical order docs/system: Document Arm Versatile Express boards docs/system: Document the various MPS2 models docs/system: Document Musca boards linux-user/arm: BKPT should cause SIGTRAP, not be a syscall linux-user/arm: Remove bogus SVC 0xf0002 handling linux-user/arm: Handle invalid arm-specific syscalls correctly linux-user/arm: Fix identification of syscall numbers target/arm: Remove unused GEN_NEON_INTEGER_OP macro target/arm: Allow user-mode code to write CPSR.E via MSR linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 Philippe Mathieu-Daudé (4): hw/arm/integratorcp: Replace hw_error() by qemu_log_mask() hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask() hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask() hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask() Richard Henderson (2): target/arm: Use tcg_gen_gvec_mov for clear_vec_high target/arm: Use clear_vec_high more effectively Thomas Huth (1): tests/acceptance: Add a test for the canon-a1100 machine docs/system/arm/integratorcp.rst | 4 +- docs/system/arm/mps2.rst | 29 +++ docs/system/arm/musca.rst | 31 +++ docs/system/arm/vexpress.rst | 60 ++ docs/system/target-arm.rst | 20 +- include/hw/arm/fsl-imx25.h | 5 + include/hw/arm/fsl-imx31.h | 4 + include/hw/arm/fsl-imx6.h | 2 +- include/hw/arm/fsl-imx6ul.h| 2 +- include/hw/arm/fsl-imx7.h | 23 ++- include/hw/misc/imx2_wdt.h | 33 include/hw/watchdog/wdt_imx2.h | 90 + target/arm/cpu.h | 2 +- hw/arm/fsl-imx25.c | 10 + hw/arm/fsl-imx31.c | 6 + hw/arm/fsl-imx6.c | 9 + hw/arm/fsl-imx6ul.c| 10 + hw/arm/fsl-imx7.c | 35 hw/arm/integratorcp.c | 23 ++- hw/arm/pxa2xx_gpio.c | 7 +- hw/char/xilinx_uartlite.c | 5 +- hw/display/pxa2xx_lcd.c| 8 +- hw/dma/pxa2xx_dma.c| 14 +- hw/gpio/pl061.c| 12 +- hw/misc/imx2_wdt.c | 90 - hw/timer/exynos4210_mct.c | 12 +- hw/watchdog/wdt_imx2.c | 303 + linux-user/arm/cpu_loop.c | 145 -- linux-user/arm/signal.c| 15 +- target/arm/translate-a64.c | 63 +++--- target/arm/translate.c | 23 --- MAINTAINERS| 6 + hw/arm/Kconfig | 5 + hw/misc/Makefile.objs
Re: [Qemu-devel] [PULL 00/29] target-arm queue
On Fri, 16 Aug 2019 at 14:17, Peter Maydell wrote: > > First arm pullreq of 4.2... > > thanks > -- PMM > > The following changes since commit 27608c7c66bd923eb5e5faab80e795408cbe2b51: > > Merge remote-tracking branch > 'remotes/dgilbert/tags/pull-migration-20190814a' into staging (2019-08-16 > 12:00:18 +0100) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20190816 > > for you to fetch changes up to 664b7e3b97d6376f3329986c465b3782458b0f8b: > > target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word (2019-08-16 > 14:02:53 +0100) > > > target-arm queue: > * target/arm: generate a custom MIDR for -cpu max > * hw/misc/zynq_slcr: refactor to use standard register definition > * Set ENET_BD_BDU in I.MX FEC controller > * target/arm: Fix routing of singlestep exceptions > * refactor a32/t32 decoder handling of PC > * minor optimisations/cleanups of some a32/t32 codegen > * target/arm/cpu64: Ensure kvm really supports aarch64=off > * target/arm/cpu: Ensure we can use the pmu with kvm > * target/arm: Minor cleanups preparatory to KVM SVE support > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2 for any user-visible changes. -- PMM
[Qemu-devel] [PULL 00/29] target-arm queue
First arm pullreq of 4.2... thanks -- PMM The following changes since commit 27608c7c66bd923eb5e5faab80e795408cbe2b51: Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20190814a' into staging (2019-08-16 12:00:18 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190816 for you to fetch changes up to 664b7e3b97d6376f3329986c465b3782458b0f8b: target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word (2019-08-16 14:02:53 +0100) target-arm queue: * target/arm: generate a custom MIDR for -cpu max * hw/misc/zynq_slcr: refactor to use standard register definition * Set ENET_BD_BDU in I.MX FEC controller * target/arm: Fix routing of singlestep exceptions * refactor a32/t32 decoder handling of PC * minor optimisations/cleanups of some a32/t32 codegen * target/arm/cpu64: Ensure kvm really supports aarch64=off * target/arm/cpu: Ensure we can use the pmu with kvm * target/arm: Minor cleanups preparatory to KVM SVE support Aaron Hill (1): Set ENET_BD_BDU in I.MX FEC controller Alex Bennée (1): target/arm: generate a custom MIDR for -cpu max Andrew Jones (6): target/arm/cpu64: Ensure kvm really supports aarch64=off target/arm/cpu: Ensure we can use the pmu with kvm target/arm/helper: zcr: Add build bug next to value range assumption target/arm/cpu: Use div-round-up to determine predicate register array size target/arm/kvm64: Fix error returns target/arm/kvm64: Move the get/put of fpsimd registers out Damien Hedde (1): hw/misc/zynq_slcr: use standard register definition Peter Maydell (2): target/arm: Factor out 'generate singlestep exception' function target/arm: Fix routing of singlestep exceptions Richard Henderson (18): target/arm: Pass in pc to thumb_insn_is_16bit target/arm: Introduce pc_curr target/arm: Introduce read_pc target/arm: Introduce add_reg_for_lit target/arm: Remove redundant s->pc & ~1 target/arm: Replace s->pc with s->base.pc_next target/arm: Replace offset with pc in gen_exception_insn target/arm: Replace offset with pc in gen_exception_internal_insn target/arm: Remove offset argument to gen_exception_bkpt_insn target/arm: Use unallocated_encoding for aarch32 target/arm: Remove helper_double_saturate target/arm: Use tcg_gen_extract_i32 for shifter_out_im target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB target/arm: Remove redundant shift tests target/arm: Use ror32 instead of open-coding the operation target/arm: Use tcg_gen_rotri_i32 for gen_swap_half target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word target/arm/cpu.h | 13 +- target/arm/helper.h| 1 - target/arm/kvm_arm.h | 28 ++ target/arm/translate-a64.h | 4 +- target/arm/translate.h | 39 ++- hw/misc/zynq_slcr.c| 450 hw/net/imx_fec.c | 4 + target/arm/cpu.c | 30 ++- target/arm/cpu64.c | 31 ++- target/arm/helper.c| 7 + target/arm/kvm.c | 7 + target/arm/kvm64.c | 161 +++- target/arm/op_helper.c | 15 -- target/arm/translate-a64.c | 130 -- target/arm/translate-vfp.inc.c | 45 +--- target/arm/translate.c | 572 + 16 files changed, 771 insertions(+), 766 deletions(-)
Re: [Qemu-devel] [PULL 00/29] target-arm queue
On 8 February 2014 15:57, Peter Maydell wrote: > Pull request for the target-arm queue... > > thanks > -- PMM > > The following changes since commit 3ea3bd62451ac79478b440ad9fe2a4cd69783a1f: > > Merge remote-tracking branch > 'remotes/juanquintela/tags/migration/20140204-1' into staging (2014-02-08 > 13:12:50 +) > > are available in the git repository at: > > > git://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20140208 > > for you to fetch changes up to 69991d7dcbcf7f3fe38274bc67fcba3cbbfda0cf > > arm/zynq: Add software system reset via SCLR (2014-02-08 14:50:48 +) Applied, thanks. -- PMM
[Qemu-devel] [PULL 00/29] target-arm queue
Pull request for the target-arm queue... thanks -- PMM The following changes since commit 3ea3bd62451ac79478b440ad9fe2a4cd69783a1f: Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20140204-1' into staging (2014-02-08 13:12:50 +) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140208 for you to fetch changes up to 69991d7dcbcf7f3fe38274bc67fcba3cbbfda0cf: arm/zynq: Add software system reset via SCLR (2014-02-08 14:50:48 +) target-arm queue: * more A64 Neon instructions * AArch32 VCVTB and VCVTT ARMv8 instructions * fixes to inaccuracies in GIC emulation * libvixl disassembler for A64 * Allwinner SoC ethernet controller * zynq software system reset support Alex Bennée (1): target-arm: A64: Add 2-reg-misc REV* instructions Beniamino Galvani (4): util/fifo8: implement push/pop of multiple bytes util/fifo8: clear fifo head upon reset hw/net: add support for Allwinner EMAC Fast Ethernet controller hw/arm/allwinner-a10: initialize EMAC Christoffer Dall (5): arm_gic: Fix GIC pending behavior arm_gic: Keep track of SGI sources arm_gic: Support setting/getting binary point reg vmstate: Add uint32 2D-array support arm_gic: Add GICC_APRn state to the GICState Claudio Fontana (1): disas: Implement disassembly output for A64 Peter Maydell (16): target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR target-arm: A64: Implement scalar pairwise ops target-arm: A64: Implement remaining integer scalar-3-same insns target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc target-arm: A64: Add skeleton decode for SIMD 2-reg misc group target-arm: A64: Implement 2-register misc compares, ABS, NEG target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT target-arm: A64: Add narrowing 2-reg-misc instructions target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group rules.mak: Support .cc as a C++ source file suffix rules.mak: Link with C++ if we have a C++ compiler disas: Add subset of libvixl sources for A64 disassembler disas/libvixl: Fix upstream libvixl compilation issues Sebastian Huber (1): arm/zynq: Add software system reset via SCLR Will Newton (1): target-arm: Add support for AArch32 64bit VCVTB and VCVTT configure |4 + default-configs/arm-softmmu.mak |1 + disas.c | 14 +- disas/Makefile.objs |5 + disas/arm-a64.cc | 87 ++ disas/libvixl/LICENCE | 30 + disas/libvixl/Makefile.objs |8 + disas/libvixl/README | 12 + disas/libvixl/a64/assembler-a64.h | 1784 + disas/libvixl/a64/constants-a64.h | 1104 disas/libvixl/a64/cpu-a64.h | 56 ++ disas/libvixl/a64/decoder-a64.cc | 712 + disas/libvixl/a64/decoder-a64.h | 198 disas/libvixl/a64/disasm-a64.cc | 1678 +++ disas/libvixl/a64/disasm-a64.h| 109 ++ disas/libvixl/a64/instructions-a64.cc | 238 + disas/libvixl/a64/instructions-a64.h | 344 +++ disas/libvixl/globals.h | 65 ++ disas/libvixl/platform.h | 43 + disas/libvixl/utils.cc| 120 +++ disas/libvixl/utils.h | 126 +++ hw/arm/allwinner-a10.c| 16 + hw/arm/cubieboard.c | 11 +- hw/intc/arm_gic.c | 179 +++- hw/intc/arm_gic_common.c |8 +- hw/intc/gic_internal.h| 16 +- hw/misc/zynq_slcr.c |5 + hw/net/Makefile.objs |1 + hw/net/allwinner_emac.c | 539 ++ include/disas/bfd.h |1 + include/hw/arm/allwinner-a10.h|3 + include/hw/intc/arm_gic_common.h | 33 + include/hw/net/allwinner_emac.h | 210 include/migration/vmstate.h |6 + include/qemu/fifo8.h | 61 ++ rules.mak | 14 +- target-arm/helper.h |1 + target-arm/neon_helper.c | 12 + target-arm/translate-a64.c| 1213 -- target-arm/translate.c| 83 +- tcg/tcg.h |3 + util/fifo8.c | 47 + 42 files changed, 9044 insertions(+)
