Re: [PULL 00/30] tcg patch queue

2022-03-04 Thread Richard Henderson 

On 3/4/22 05:22, Peter Maydell wrote:

This causes the linux-user tests to fail on the aarch64 host:
https://gitlab.com/qemu-project/qemu/-/jobs/2163919769

All the qemu-i386 invocations fail like this:

timeout --foreground 90
/home/gitlab-runner/builds/CMuZxyfG/0/qemu-project/qemu/build/qemu-i386
sigbus > sigbus.out
qemu-i386: Unable to reserve 0x1 bytes of virtual address
space at 0x8000 (File exists) for use as guest address space (check
your virtual memory ulimit setting, min_mmap_addr or reserve less
using -R option)


Hmm.  It works when run standalone on aarch64.ci.qemu.org, so it must be something within 
the ci environment.  Alex, any idea how to replicate this?



r~

Re: [PULL 00/30] tcg patch queue

2022-03-04 Thread Peter Maydell 
On Thu, 3 Mar 2022 at 20:59, Richard Henderson
 wrote:
>
> The following changes since commit 36eae3a732a1f2aa81391e871ac0e9bb3233e7d7:
>
>   Merge remote-tracking branch 
> 'remotes/dgilbert-gitlab/tags/pull-migration-20220302b' into staging 
> (2022-03-02 20:55:48 +)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220303
>
> for you to fetch changes up to f23e6de25c31cadd9a3b7122f9384e6b259ce37f:
>
>   tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32 (2022-03-03 10:47:20 
> -1000)
>
> 
> Reorder do_constant_folding_cond test to satisfy valgrind.
> Fix value of MAX_OPC_PARAM_IARGS.
> Add opcodes for vector nand, nor, eqv.
> Support vector nand, nor, eqv on PPC and S390X hosts.
> Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.
> Support 32-bit guest addresses as signed values.
>

This causes the linux-user tests to fail on the aarch64 host:
https://gitlab.com/qemu-project/qemu/-/jobs/2163919769

All the qemu-i386 invocations fail like this:

timeout --foreground 90
/home/gitlab-runner/builds/CMuZxyfG/0/qemu-project/qemu/build/qemu-i386
sigbus > sigbus.out
qemu-i386: Unable to reserve 0x1 bytes of virtual address
space at 0x8000 (File exists) for use as guest address space (check
your virtual memory ulimit setting, min_mmap_addr or reserve less
using -R option)

The build-oss-fuzz test also failed with a timeout, but it
has a habit of doing that so could be unrelated to these changes:
https://gitlab.com/qemu-project/qemu/-/jobs/2163919743


thanks
-- PMM

[PULL 00/30] tcg patch queue

2022-03-03 Thread Richard Henderson 
The following changes since commit 36eae3a732a1f2aa81391e871ac0e9bb3233e7d7:

  Merge remote-tracking branch 
'remotes/dgilbert-gitlab/tags/pull-migration-20220302b' into staging 
(2022-03-02 20:55:48 +)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220303

for you to fetch changes up to f23e6de25c31cadd9a3b7122f9384e6b259ce37f:

  tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32 (2022-03-03 10:47:20 -1000)


Reorder do_constant_folding_cond test to satisfy valgrind.
Fix value of MAX_OPC_PARAM_IARGS.
Add opcodes for vector nand, nor, eqv.
Support vector nand, nor, eqv on PPC and S390X hosts.
Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.
Support 32-bit guest addresses as signed values.


Alex Bennée (1):
  tcg/optimize: only read val after const check

Richard Henderson (28):
  tcg: Add opcodes for vector nand, nor, eqv
  tcg/ppc: Implement vector NAND, NOR, EQV
  tcg/s390x: Implement vector NAND, NOR, EQV
  tcg/i386: Detect AVX512
  tcg/i386: Add tcg_out_evex_opc
  tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
  tcg/i386: Implement avx512 variable shifts
  tcg/i386: Implement avx512 scalar shift
  tcg/i386: Implement avx512 immediate sari shift
  tcg/i386: Implement avx512 immediate rotate
  tcg/i386: Implement avx512 variable rotate
  tcg/i386: Support avx512vbmi2 vector shift-double instructions
  tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
  tcg/i386: Remove rotls_vec from tcg_target_op_def
  tcg/i386: Expand scalar rotate with avx512 insns
  tcg/i386: Implement avx512 min/max/abs
  tcg/i386: Implement avx512 multiply
  tcg/i386: Implement more logical operations for avx512
  tcg/i386: Implement bitsel for avx512
  tcg: Add TCG_TARGET_SIGNED_ADDR32
  accel/tcg: Split out g2h_tlbe
  accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu
  accel/tcg: Add guest_base_signed_addr32 for user-only
  linux-user: Support TCG_TARGET_SIGNED_ADDR32
  tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32
  tcg/mips: Support TCG_TARGET_SIGNED_ADDR32
  tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32
  tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32

Ziqiao Kong (1):
  tcg: Set MAX_OPC_PARAM_IARGS to 7

 include/exec/cpu-all.h|  20 +-
 include/exec/cpu_ldst.h   |   3 +-
 include/qemu/cpuid.h  |  20 +-
 include/tcg/tcg-opc.h |   3 +
 include/tcg/tcg.h |   5 +-
 tcg/aarch64/tcg-target-sa32.h |   7 +
 tcg/aarch64/tcg-target.h  |   3 +
 tcg/arm/tcg-target-sa32.h |   1 +
 tcg/arm/tcg-target.h  |   3 +
 tcg/i386/tcg-target-con-set.h |   1 +
 tcg/i386/tcg-target-sa32.h|   1 +
 tcg/i386/tcg-target.h |  17 +-
 tcg/i386/tcg-target.opc.h |   3 +
 tcg/loongarch64/tcg-target-sa32.h |   1 +
 tcg/mips/tcg-target-sa32.h|   9 +
 tcg/ppc/tcg-target-sa32.h |   1 +
 tcg/ppc/tcg-target.h  |   3 +
 tcg/riscv/tcg-target-sa32.h   |   5 +
 tcg/s390x/tcg-target-sa32.h   |   1 +
 tcg/s390x/tcg-target.h|   3 +
 tcg/sparc/tcg-target-sa32.h   |   1 +
 tcg/tci/tcg-target-sa32.h |   1 +
 accel/tcg/cputlb.c|  36 ++--
 bsd-user/main.c   |   4 +
 linux-user/elfload.c  |  62 --
 linux-user/main.c |   3 +
 tcg/optimize.c|  20 +-
 tcg/tcg-op-vec.c  |  27 ++-
 tcg/tcg.c |  10 +
 tcg/aarch64/tcg-target.c.inc  |  81 +---
 tcg/i386/tcg-target.c.inc | 387 +++---
 tcg/loongarch64/tcg-target.c.inc  |  15 +-
 tcg/mips/tcg-target.c.inc |  10 +-
 tcg/ppc/tcg-target.c.inc  |  15 ++
 tcg/riscv/tcg-target.c.inc|   8 +-
 tcg/s390x/tcg-target.c.inc|  17 ++
 tcg/tci/tcg-target.c.inc  |   2 +-
 37 files changed, 640 insertions(+), 169 deletions(-)
 create mode 100644 tcg/aarch64/tcg-target-sa32.h
 create mode 100644 tcg/arm/tcg-target-sa32.h
 create mode 100644 tcg/i386/tcg-target-sa32.h
 create mode 100644 tcg/loongarch64/tcg-target-sa32.h
 create mode 100644 tcg/mips/tcg-target-sa32.h
 create mode 100644 tcg/ppc/tcg-target-sa32.h
 create mode 100644 tcg/riscv/tcg-target-sa32.h
 create mode 100644 tcg/s390x/tcg-target-sa32.h
 create mode 100644 tcg/sparc/tcg-target-sa32.h
 create mode 100644 tcg/tci/tcg-target-sa32.h