Re: [PULL 00/40] riscv-to-apply queue
On Wed, Feb 16, 2022 at 11:59 AM Alistair Francis wrote:
>
> On Tue, Feb 15, 2022 at 9:39 PM Peter Maydell
> wrote:
> >
> > On Sat, 12 Feb 2022 at 00:07, Alistair Francis
> > wrote:
> > >
> > > From: Alistair Francis
> > >
> > > The following changes since commit
> > > 0a301624c2f4ced3331ffd5bce85b4274fe132af:
> > >
> > > Merge remote-tracking branch
> > > 'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08
> > > 11:40:08 +)
> > >
> > > are available in the Git repository at:
> > >
> > > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220212
> > >
> > > for you to fetch changes up to 31d69b66ed89fa0f66d4e5a15e9664c92c3ed8f8:
> > >
> > > docs/system: riscv: Update description of CPU (2022-02-11 18:31:29
> > > +1000)
> > >
> > >
> > > Fourth RISC-V PR for QEMU 7.0
> > >
> > > * Remove old Ibex PLIC header file
> > > * Allow writing 8 bytes with generic loader
> > > * Fixes for RV128
> > > * Refactor RISC-V CPU configs
> > > * Initial support for XVentanaCondOps custom extension
> > > * Fix for vill field in vtype
> > > * Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
> > > * RISC-V AIA support for virt machine
> > > * Support for svnapot, svinval and svpbmt extensions
> >
> > Hi; this has format string issues on 32-bit hosts:
> > https://gitlab.com/qemu-project/qemu/-/jobs/2092600735
> >
> > ../hw/riscv/virt.c: In function 'create_fdt_imsic':
> > ../hw/riscv/virt.c:519:49: error: format '%lx' expects argument of
> > type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long
> > long unsigned int'} [-Werror=format=]
> >
> > ../hw/riscv/virt.c:569:49: error: format '%lx' expects argument of
> > type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long
> > long unsigned int'} [-Werror=format=]
> >
> > Printing hwaddrs needs the HWADDR_PRIx macro. (%l and %ll are
> > usually the wrong thing in QEMU code as we don't often deal
> > with real 'long' or 'long long' types.)
>
> Argh... Sorry about that Peter.
>
> I have already fixed a few issues with that series and I would like
> this PR merged soon, so I have just dropped the offending patches.
>
> @Anup Patel You will need to rebase the last 5 or so AIA patches, fix
> the failures and re-send them once the v2 PR is merged.
Okay, I will re-send.
Thanks,
Anup
>
> Alistair
>
> >
> > -- PMM
Re: [PULL 00/40] riscv-to-apply queue
On Tue, Feb 15, 2022 at 9:39 PM Peter Maydell wrote:
>
> On Sat, 12 Feb 2022 at 00:07, Alistair Francis
> wrote:
> >
> > From: Alistair Francis
> >
> > The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af:
> >
> > Merge remote-tracking branch
> > 'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08
> > 11:40:08 +)
> >
> > are available in the Git repository at:
> >
> > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220212
> >
> > for you to fetch changes up to 31d69b66ed89fa0f66d4e5a15e9664c92c3ed8f8:
> >
> > docs/system: riscv: Update description of CPU (2022-02-11 18:31:29 +1000)
> >
> >
> > Fourth RISC-V PR for QEMU 7.0
> >
> > * Remove old Ibex PLIC header file
> > * Allow writing 8 bytes with generic loader
> > * Fixes for RV128
> > * Refactor RISC-V CPU configs
> > * Initial support for XVentanaCondOps custom extension
> > * Fix for vill field in vtype
> > * Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
> > * RISC-V AIA support for virt machine
> > * Support for svnapot, svinval and svpbmt extensions
>
> Hi; this has format string issues on 32-bit hosts:
> https://gitlab.com/qemu-project/qemu/-/jobs/2092600735
>
> ../hw/riscv/virt.c: In function 'create_fdt_imsic':
> ../hw/riscv/virt.c:519:49: error: format '%lx' expects argument of
> type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long
> long unsigned int'} [-Werror=format=]
>
> ../hw/riscv/virt.c:569:49: error: format '%lx' expects argument of
> type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long
> long unsigned int'} [-Werror=format=]
>
> Printing hwaddrs needs the HWADDR_PRIx macro. (%l and %ll are
> usually the wrong thing in QEMU code as we don't often deal
> with real 'long' or 'long long' types.)
Argh... Sorry about that Peter.
I have already fixed a few issues with that series and I would like
this PR merged soon, so I have just dropped the offending patches.
@Anup Patel You will need to rebase the last 5 or so AIA patches, fix
the failures and re-send them once the v2 PR is merged.
Alistair
>
> -- PMM
Re: [PULL 00/40] riscv-to-apply queue
On Sat, 12 Feb 2022 at 00:07, Alistair Francis
wrote:
>
> From: Alistair Francis
>
> The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08
> 11:40:08 +)
>
> are available in the Git repository at:
>
> g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220212
>
> for you to fetch changes up to 31d69b66ed89fa0f66d4e5a15e9664c92c3ed8f8:
>
> docs/system: riscv: Update description of CPU (2022-02-11 18:31:29 +1000)
>
>
> Fourth RISC-V PR for QEMU 7.0
>
> * Remove old Ibex PLIC header file
> * Allow writing 8 bytes with generic loader
> * Fixes for RV128
> * Refactor RISC-V CPU configs
> * Initial support for XVentanaCondOps custom extension
> * Fix for vill field in vtype
> * Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
> * RISC-V AIA support for virt machine
> * Support for svnapot, svinval and svpbmt extensions
Hi; this has format string issues on 32-bit hosts:
https://gitlab.com/qemu-project/qemu/-/jobs/2092600735
../hw/riscv/virt.c: In function 'create_fdt_imsic':
../hw/riscv/virt.c:519:49: error: format '%lx' expects argument of
type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long
long unsigned int'} [-Werror=format=]
../hw/riscv/virt.c:569:49: error: format '%lx' expects argument of
type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long
long unsigned int'} [-Werror=format=]
Printing hwaddrs needs the HWADDR_PRIx macro. (%l and %ll are
usually the wrong thing in QEMU code as we don't often deal
with real 'long' or 'long long' types.)
-- PMM
[PULL 00/40] riscv-to-apply queue
From: Alistair Francis The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08 11:40:08 +) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220212 for you to fetch changes up to 31d69b66ed89fa0f66d4e5a15e9664c92c3ed8f8: docs/system: riscv: Update description of CPU (2022-02-11 18:31:29 +1000) Fourth RISC-V PR for QEMU 7.0 * Remove old Ibex PLIC header file * Allow writing 8 bytes with generic loader * Fixes for RV128 * Refactor RISC-V CPU configs * Initial support for XVentanaCondOps custom extension * Fix for vill field in vtype * Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode * RISC-V AIA support for virt machine * Support for svnapot, svinval and svpbmt extensions Anup Patel (23): target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode target/riscv: Implement SGEIP bit in hip and hie CSRs target/riscv: Implement hgeie and hgeip CSRs target/riscv: Improve delivery of guest external interrupts target/riscv: Allow setting CPU feature from machine/device emulation target/riscv: Add AIA cpu feature target/riscv: Add defines for AIA CSRs target/riscv: Allow AIA device emulation to set ireg rmw callback target/riscv: Implement AIA local interrupt priorities target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 target/riscv: Implement AIA hvictl and hviprioX CSRs target/riscv: Implement AIA interrupt filtering CSRs target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs target/riscv: Implement AIA xiselect and xireg CSRs target/riscv: Implement AIA IMSIC interface CSRs hw/riscv: virt: Use AIA INTC compatible string when available target/riscv: Allow users to force enable AIA CSRs in HART hw/intc: Add RISC-V AIA APLIC device emulation hw/riscv: virt: Add optional AIA APLIC support to virt machine hw/intc: Add RISC-V AIA IMSIC device emulation hw/riscv: virt: Add optional AIA IMSIC support to virt machine docs/system: riscv: Document AIA options for virt machine hw/riscv: virt: Increase maximum number of allowed CPUs Frédéric Pétrot (1): target/riscv: correct "code should not be reached" for x-rv128 Guo Ren (1): target/riscv: Ignore reserved bits in PTE for RV64 LIU Zhiwei (1): target/riscv: Fix vill field write in vtype Petr Tesarik (1): Allow setting up to 8 bytes with the generic loader Philipp Tomsich (7): target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: access cfg structure through DisasContext target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps custom extension target/riscv: add a MAINTAINERS entry for XVentanaCondOps Weiwei Li (4): target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE target/riscv: add support for svnapot extension target/riscv: add support for svinval extension target/riscv: add support for svpbmt extension Wilfred Mallawa (1): include: hw: remove ibex_plic.h Yu Li (1): docs/system: riscv: Update description of CPU docs/system/riscv/virt.rst | 22 +- include/hw/intc/ibex_plic.h| 67 - include/hw/intc/riscv_aplic.h | 79 ++ include/hw/intc/riscv_imsic.h | 68 ++ include/hw/riscv/virt.h| 41 +- target/riscv/cpu.h | 169 ++- target/riscv/cpu_bits.h| 129 ++ target/riscv/XVentanaCondOps.decode| 25 + target/riscv/insn32.decode |7 + hw/core/generic-loader.c |2 +- hw/intc/riscv_aplic.c | 978 +++ hw/intc/riscv_imsic.c | 448 +++ hw/riscv/virt.c| 712 +-- target/riscv/cpu.c | 113 +- target/riscv/cpu_helper.c | 377 +- target/riscv/csr.c | 1282 ++-- target/riscv/gdbstub.c |3 + target/riscv/machine.c | 24 +- target/riscv/translate.c | 61 +- target/riscv/vector_helper.c |1 + target/riscv/insn_trans/trans_rvb.c.inc|8 +-
