Re: [PULL 00/72] ppc-for-9.1-1 queue
On 5/23/24 16:53, Nicholas Piggin wrote: This replaces the previous PR for tags/pull-ppc-for-9.1-1-20240524 note this tag is tags/pull-ppc-for-9.1-1-20240524-1 (added -1 suffix). The changelog and code are unchanged. Subject for BHRB patches are fixed and trimmed for some MMU cleanup patches. So I won't re-send individual patches to lists. Thanks, Nick The following changes since commit 70581940cabcc51b329652becddfbc6a261b1b83: Merge tag 'pull-tcg-20240523' ofhttps://gitlab.com/rth7680/qemu into staging (2024-05-23 09:47:40 -0700) are available in the Git repository at: https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.1-1-20240524-1 for you to fetch changes up to e48fb4c590a23d81ee1d2f09ee9bcf5dd5f98e43: target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot() (2024-05-24 09:43:14 +1000) * Fix an interesting TLB invalidate race * Implement more instructions with decodetree * Add the POWER8/9/10 BHRB facility * Add missing instructions, registers, SMT support * First round of a big MMU xlate cleanup Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~
[PULL 00/72] ppc-for-9.1-1 queue
This replaces the previous PR for tags/pull-ppc-for-9.1-1-20240524 note
this tag is tags/pull-ppc-for-9.1-1-20240524-1 (added -1 suffix). The
changelog and code are unchanged. Subject for BHRB patches are fixed
and trimmed for some MMU cleanup patches. So I won't re-send individual
patches to lists.
Thanks,
Nick
The following changes since commit 70581940cabcc51b329652becddfbc6a261b1b83:
Merge tag 'pull-tcg-20240523' of https://gitlab.com/rth7680/qemu into staging
(2024-05-23 09:47:40 -0700)
are available in the Git repository at:
https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.1-1-20240524-1
for you to fetch changes up to e48fb4c590a23d81ee1d2f09ee9bcf5dd5f98e43:
target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot() (2024-05-24
09:43:14 +1000)
* Fix an interesting TLB invalidate race
* Implement more instructions with decodetree
* Add the POWER8/9/10 BHRB facility
* Add missing instructions, registers, SMT support
* First round of a big MMU xlate cleanup
BALATON Zoltan (33):
target/ppc: Remove unused helper_rac()
target/ppc: Move calculation of a value closer to its usage in booke tlb
checks
target/ppc: Remove unneeded local variable from booke tlb checks
target/ppc: Simplify checking for real mode in get_physical_address_wtlb()
target/ppc: Drop cases for unimplemented MPC8xx MMU
target/ppc: Introduce mmu6xx_get_physical_address()
target/ppc: Move else branch to avoid large if block in
mmu6xx_get_physical_address()
target/ppc: Move some debug logging in ppc6xx_tlb_check()
target/ppc: Eliminate ret from mmu6xx_get_physical_address()
target/ppc: Split out BookE xlate cases before checking real mode
target/ppc: Split off real mode cases in get_physical_address_wtlb()
target/ppc: Inline and remove check_physical()
target/ppc: Fix misindented qemu_log_mask() calls
target/ppc: Deindent ppc_jumbo_xlate()
target/ppc: Replace hard coded constants in ppc_jumbo_xlate()
target/ppc: Don't use mmu_ctx_t for mmu40x_get_physical_address()
target/ppc: Don't use mmu_ctx_t in mmubooke_get_physical_address()
target/ppc: Don't use mmu_ctx_t in mmubooke206_get_physical_address()
target/ppc: Remove BookE from direct store handling
target/ppc: Split off BookE handling from ppc_jumbo_xlate()
target/ppc: Simplify ppc_booke_xlate() part 1
target/ppc: Simplify ppc_booke_xlate() part 2
target/ppc: Split off real mode handling from get_physical_address_wtlb()
target/ppc: Split off 40x cases from ppc_jumbo_xlate()
target/ppc: Transform ppc_jumbo_xlate() into ppc_6xx_xlate()
target/ppc: Move mmu_ctx_t type to mmu_common.c
target/ppc: Remove id_tlbs flag from CPU env
target/ppc: Split off common embedded TLB init
target/ppc/mmu-hash32.c: Drop a local variable
target/ppc/mmu-radix64.c: Drop a local variable
target/ppc: Add a function to check for page protection bit
target/ppc: Move out BookE and related MMU functions from mmu_common.c
target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot()
Chinmay Rath (13):
target/ppc: Merge various fpu helpers
target/ppc: Move floating-point arithmetic instructions to decodetree.
target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree.
target/ppc: Make divw[u] handler method decodetree compatible.
target/ppc: Move divw[u, e, eu] instructions to decodetree.
target/ppc: Move neg, darn, mod{sw, uw} to decodetree.
target/ppc: Move multiply fixed-point insns (64-bit operands) to
decodetree.
target/ppc: Move div/mod fixed-point insns (64 bits operands) to
decodetree.
target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions to
decodetree.
target/ppc: Move logical fixed-point instructions to decodetree.
target/ppc: Move VMX storage access instructions to decodetree
target/ppc: Move VMX integer logical instructions to decodetree.
target/ppc: Move VMX integer max/min instructions to decodetree.
Dr. David Alan Gilbert (1):
target/ppc: Remove unused struct 'mmu_ctx_hash32'
Glenn Miles (4):
target/ppc: Add new hflags to support BHRB
target/ppc: Add recording of taken branches to BHRB
target/ppc: Add clrbhrb and mfbhrbe instructions
target/ppc: Add migration support for BHRB
Nicholas Piggin (21):
spapr: avoid overhead of finding vhyp class in critical operations
ppc/spapr: Add ibm,pi-features
target/ppc: Fix broadcast tlbie synchronisation
tcg/cputlb: Remove non-synced variants of global TLB flushes
tcg/cputlb: remove other-cpu capability from TLB flushing
target/ppc: Move sync instructions to decodetree
target/ppc: Fix embedded memory barriers
target/ppc: Add ISA v3.1 varian
Re: [PULL 00/72] ppc-for-9.1-1 queue
On Fri May 24, 2024 at 9:06 AM AEST, Nicholas Piggin wrote: > The following changes since commit 70581940cabcc51b329652becddfbc6a261b1b83: > > Merge tag 'pull-tcg-20240523' of https://gitlab.com/rth7680/qemu into > staging (2024-05-23 09:47:40 -0700) > > are available in the Git repository at: > > https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.1-1-20240524 [snip] > Glenn Miles (4): > This commit is preparatory to the addition of Branch History Rolling > Buffer (BHRB) functionality, which is being provided today starting with the > P8 processor. > This commit continues adding support for the Branch History Rolling > Buffer (BHRB) as is provided starting with the P8 processor and continuing > with its successors. This commit is limited to the recording and filtering > of taken branches. > Add support for the clrbhrb and mfbhrbe instructions. > Adds migration support for Branch History Rolling Buffer (BHRB) > internal state. The BHRB patch subject lines have gone haywire and I didn't notice before now. Probably my fault. Hold off and I will fix and give a new tag to pull. Thanks, Nick
[PULL 00/72] ppc-for-9.1-1 queue
The following changes since commit 70581940cabcc51b329652becddfbc6a261b1b83:
Merge tag 'pull-tcg-20240523' of https://gitlab.com/rth7680/qemu into staging
(2024-05-23 09:47:40 -0700)
are available in the Git repository at:
https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.1-1-20240524
for you to fetch changes up to 4e0e22a2de927ec827e3464f7aedd47ed22268d2:
target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot() (2024-05-24
08:57:51 +1000)
* Fix an interesting TLB invalidate race
* Implement more instructions with decodetree
* Add the POWER8/9/10 BHRB facility
* Add missing instructions, registers, SMT support
* First round of a big MMU xlate cleanup
BALATON Zoltan (33):
target/ppc: Remove unused helper
target/ppc/mmu_common.c: Move calculation of a value closer to its usage
target/ppc/mmu_common.c: Remove unneeded local variable
target/ppc/mmu_common.c: Simplify checking for real mode
target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU
target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address()
target/ppc/mmu_common.c: Move else branch to avoid large if block
target/ppc/mmu_common.c: Move some debug logging
target/ppc/mmu_common.c: Eliminate ret from mmu6xx_get_physical_address()
target/ppc/mmu_common.c: Split out BookE cases before checking real mode
target/ppc/mmu_common.c: Split off real mode cases in
get_physical_address_wtlb()
target/ppc/mmu_common.c: Inline and remove check_physical()
target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls
target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate()
target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate()
target/ppc/mmu_common.c: Don't use mmu_ctx_t for
mmu40x_get_physical_address()
target/ppc/mmu_common.c: Don't use mmu_ctx_t in
mmubooke_get_physical_address()
target/ppc/mmu_common.c: Don't use mmu_ctx_t in
mmubooke206_get_physical_address()
target/ppc/mmu_common.c: Remove BookE from direct store handling
target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate()
target/ppc/mmu_common.c: Simplify ppc_booke_xlate() part 1
target/ppc/mmu_common.c: Simplify ppc_booke_xlate() part 2
target/ppc/mmu_common.c: Split off real mode handling from
get_physical_address_wtlb()
target/ppc/mmu_common.c: Split off 40x cases from ppc_jumbo_xlate()
target/ppc/mmu_common.c: Transform ppc_jumbo_xlate() into ppc_6xx_xlate()
target/ppc/mmu_common.c: Move mmu_ctx_t type to mmu_common.c
target/ppc: Remove id_tlbs flag from CPU env
target/ppc: Split off common embedded TLB init
target/ppc/mmu-hash32.c: Drop a local variable
target/ppc/mmu-radix64.c: Drop a local variable
target/ppc: Add a function to check for page protection bit
target/ppc: Move out BookE and related MMU functions from mmu_common.c
target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot()
Chinmay Rath (13):
target/ppc: Merge various fpu helpers
target/ppc: Move floating-point arithmetic instructions to decodetree.
target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree.
target/ppc: Make divw[u] handler method decodetree compatible.
target/ppc: Move divw[u, e, eu] instructions to decodetree.
target/ppc: Move neg, darn, mod{sw, uw} to decodetree.
target/ppc: Move multiply fixed-point insns (64-bit operands) to
decodetree.
target/ppc: Move div/mod fixed-point insns (64 bits operands) to
decodetree.
target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions to
decodetree.
target/ppc: Move logical fixed-point instructions to decodetree.
target/ppc: Move VMX storage access instructions to decodetree
target/ppc: Move VMX integer logical instructions to decodetree.
target/ppc: Move VMX integer max/min instructions to decodetree.
Dr. David Alan Gilbert (1):
target/ppc: Remove unused struct 'mmu_ctx_hash32'
Glenn Miles (4):
This commit is preparatory to the addition of Branch History Rolling
Buffer (BHRB) functionality, which is being provided today starting with the P8
processor.
This commit continues adding support for the Branch History Rolling
Buffer (BHRB) as is provided starting with the P8 processor and continuing with
its successors. This commit is limited to the recording and filtering of taken
branches.
Add support for the clrbhrb and mfbhrbe instructions.
Adds migration support for Branch History Rolling Buffer (BHRB) internal
state.
Nicholas Piggin (21):
spapr: avoid overhead of finding vhyp class in critical operations
ppc/spapr: Add ibm,pi-features
target/ppc: Fix broadcast tlbie synchronisation
tcg/cputlb: Remove non-synced variants of gl
