[Qemu-devel] [PATCH] Sparc32: dummy implementation of MXCC MMU breakpoint registers
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, save
and load all MXCC registers.
Signed-off-by: Blue Swirl
---
v2: add save/load for all MXCC registers, fix width of breakpoint
action register
target-sparc/cpu.h |4 +++-
target-sparc/machine.c | 26 ++
target-sparc/op_helper.c | 26 --
3 files changed, 53 insertions(+), 3 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 320530e..a220bf4 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -403,6 +403,8 @@ typedef struct CPUSPARCState {
uint32_t mmuregs[32];
uint64_t mxccdata[4];
uint64_t mxccregs[8];
+uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
+uint64_t mmubpaction;
uint64_t mmubpregs[4];
uint64_t prom_addr;
#endif
@@ -521,7 +523,7 @@ int cpu_sparc_signal_handler(int host_signum, void
*pinfo, void *puc);
#define cpu_signal_handler cpu_sparc_signal_handler
#define cpu_list sparc_cpu_list
-#define CPU_SAVE_VERSION 6
+#define CPU_SAVE_VERSION 7
/* MMU modes definitions */
#if defined (TARGET_SPARC64)
diff --git a/target-sparc/machine.c b/target-sparc/machine.c
index 752e431..bae23c5 100644
--- a/target-sparc/machine.c
+++ b/target-sparc/machine.c
@@ -45,6 +45,19 @@ void cpu_save(QEMUFile *f, void *opaque)
/* MMU */
for (i = 0; i < 32; i++)
qemu_put_be32s(f, &env->mmuregs[i]);
+for (i = 0; i < 4; i++) {
+qemu_put_be64s(f, &env->mxccdata[i]);
+}
+for (i = 0; i < 8; i++) {
+qemu_put_be64s(f, &env->mxccregs[i]);
+}
+qemu_put_be32s(f, &env->mmubpctrv);
+qemu_put_be32s(f, &env->mmubpctrc);
+qemu_put_be32s(f, &env->mmubpctrs);
+qemu_put_be64s(f, &env->mmubpaction);
+for (i = 0; i < 4; i++) {
+qemu_put_be64s(f, &env->mmubpregs[i]);
+}
#else
qemu_put_be64s(f, &env->lsu);
for (i = 0; i < 16; i++) {
@@ -141,6 +154,19 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
/* MMU */
for (i = 0; i < 32; i++)
qemu_get_be32s(f, &env->mmuregs[i]);
+for (i = 0; i < 4; i++) {
+qemu_get_be64s(f, &env->mxccdata[i]);
+}
+for (i = 0; i < 8; i++) {
+qemu_get_be64s(f, &env->mxccregs[i]);
+}
+qemu_get_be32s(f, &env->mmubpctrv);
+qemu_get_be32s(f, &env->mmubpctrc);
+qemu_get_be32s(f, &env->mmubpctrs);
+qemu_get_be64s(f, &env->mmubpaction);
+for (i = 0; i < 4; i++) {
+qemu_get_be64s(f, &env->mmubpregs[i]);
+}
#else
qemu_get_be64s(f, &env->lsu);
for (i = 0; i < 16; i++) {
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index b38691e..e9cc1f5 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -1940,7 +1940,6 @@ uint64_t helper_ld_asi(target_ulong addr, int
asi, int size, int sign)
case 0x31: // Turbosparc RAM snoop
case 0x32: // Turbosparc page table descriptor diagnostic
case 0x39: /* data cache diagnostic register */
-case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
ret = 0;
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
@@ -1966,6 +1965,18 @@ uint64_t helper_ld_asi(target_ulong addr, int
asi, int size, int sign)
ret);
}
break;
+case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
+ret = env->mmubpctrv;
+break;
+case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
+ret = env->mmubpctrc;
+break;
+case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
+ret = env->mmubpctrs;
+break;
+case 0x4c: /* SuperSPARC MMU Breakpoint Action */
+ret = env->mmubpaction;
+break;
case 8: /* User code access, XXX */
default:
do_unassigned_access(addr, 0, 0, asi, size);
@@ -2304,7 +2315,6 @@ void helper_st_asi(target_ulong addr, uint64_t
val, int asi, int size)
// descriptor diagnostic
case 0x36: /* I-cache flash clear */
case 0x37: /* D-cache flash clear */
-case 0x4c: /* breakpoint action */
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
{
@@ -2328,6 +2338,18 @@ void helper_st_asi(target_ulong addr, uint64_t
val, int asi, int size)
env->mmuregs[reg]);
}
break;
+case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
+env->mmubpctrv = val & 0x;
+break;
+case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
+env->mmubpctrc = val & 0x3;
+break;
+case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
+env->mmubpctrs = val & 0x3;
+break;
+case 0x4c: /* SuperSPARC MMU Breakpoint Action */
+env->mmubpaction = val & 0x1fff;
+break;
case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
default:
--
1.6.2.4
From 10044b92f0ba0b44771b5319a82ecabf177ebf8f Mon Sep 17 0
Re: [Qemu-devel] [PATCH] Sparc32: dummy implementation of MXCC MMU breakpoint registers
Blue Swirl wrote:
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints.
Signed-off-by: Blue Swirl
---
target-sparc/cpu.h |1 +
target-sparc/op_helper.c | 26 --
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 320530e..b5d5291 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -403,6 +403,7 @@ typedef struct CPUSPARCState {
uint32_t mmuregs[32];
uint64_t mxccdata[4];
uint64_t mxccregs[8];
+uint32_t mmubpctrv, mmubpctrc, mmubpctrs, mmubpaction;
uint64_t mmubpregs[4];
uint64_t prom_addr;
#endif
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index b38691e..e9cc1f5 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -1940,7 +1940,6 @@ uint64_t helper_ld_asi(target_ulong addr, int
asi, int size, int sign)
case 0x31: // Turbosparc RAM snoop
case 0x32: // Turbosparc page table descriptor diagnostic
case 0x39: /* data cache diagnostic register */
-case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
ret = 0;
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
@@ -1966,6 +1965,18 @@ uint64_t helper_ld_asi(target_ulong addr, int
asi, int size, int sign)
ret);
}
break;
+case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
+ret = env->mmubpctrv;
+break;
+case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
+ret = env->mmubpctrc;
+break;
+case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
+ret = env->mmubpctrs;
+break;
+case 0x4c: /* SuperSPARC MMU Breakpoint Action */
+ret = env->mmubpaction;
+break;
case 8: /* User code access, XXX */
default:
do_unassigned_access(addr, 0, 0, asi, size);
@@ -2304,7 +2315,6 @@ void helper_st_asi(target_ulong addr, uint64_t
val, int asi, int size)
// descriptor diagnostic
case 0x36: /* I-cache flash clear */
case 0x37: /* D-cache flash clear */
-case 0x4c: /* breakpoint action */
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
{
@@ -2328,6 +2338,18 @@ void helper_st_asi(target_ulong addr, uint64_t
val, int asi, int size)
env->mmuregs[reg]);
}
break;
+case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
+env->mmubpctrv = val& 0x;
+break;
+case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
+env->mmubpctrc = val& 0x3;
+break;
+case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
+env->mmubpctrs = val& 0x3;
+break;
+case 0x4c: /* SuperSPARC MMU Breakpoint Action */
+env->mmubpaction = val& 0x1fff;
+break;
case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
default:
The breakpoint action register is 64 bits wide.
Re: [Qemu-devel] [PATCH] Sparc32: dummy implementation of MXCC MMU breakpoint registers
On 18 June 2011 22:45, Blue Swirl wrote:
> Add dummy registers for SuperSPARC MXCC MMU counter breakpoints.
>
> Signed-off-by: Blue Swirl
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 320530e..b5d5291 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -403,6 +403,7 @@ typedef struct CPUSPARCState {
> uint32_t mmuregs[32];
> uint64_t mxccdata[4];
> uint64_t mxccregs[8];
> + uint32_t mmubpctrv, mmubpctrc, mmubpctrs, mmubpaction;
> uint64_t mmubpregs[4];
> uint64_t prom_addr;
> #endif
Shouldn't there be a corresponding change to target-sparc/machine.c
adding these to cpu_save()/cpu_load() ? [the existing mxccdata,
mxccregs, mmubpregs don't seem to be saved/restored either...]
-- PMM
[Qemu-devel] [PATCH] Sparc32: dummy implementation of MXCC MMU breakpoint registers
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints.
Signed-off-by: Blue Swirl
---
target-sparc/cpu.h |1 +
target-sparc/op_helper.c | 26 --
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 320530e..b5d5291 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -403,6 +403,7 @@ typedef struct CPUSPARCState {
uint32_t mmuregs[32];
uint64_t mxccdata[4];
uint64_t mxccregs[8];
+uint32_t mmubpctrv, mmubpctrc, mmubpctrs, mmubpaction;
uint64_t mmubpregs[4];
uint64_t prom_addr;
#endif
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index b38691e..e9cc1f5 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -1940,7 +1940,6 @@ uint64_t helper_ld_asi(target_ulong addr, int
asi, int size, int sign)
case 0x31: // Turbosparc RAM snoop
case 0x32: // Turbosparc page table descriptor diagnostic
case 0x39: /* data cache diagnostic register */
-case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
ret = 0;
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
@@ -1966,6 +1965,18 @@ uint64_t helper_ld_asi(target_ulong addr, int
asi, int size, int sign)
ret);
}
break;
+case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
+ret = env->mmubpctrv;
+break;
+case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
+ret = env->mmubpctrc;
+break;
+case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
+ret = env->mmubpctrs;
+break;
+case 0x4c: /* SuperSPARC MMU Breakpoint Action */
+ret = env->mmubpaction;
+break;
case 8: /* User code access, XXX */
default:
do_unassigned_access(addr, 0, 0, asi, size);
@@ -2304,7 +2315,6 @@ void helper_st_asi(target_ulong addr, uint64_t
val, int asi, int size)
// descriptor diagnostic
case 0x36: /* I-cache flash clear */
case 0x37: /* D-cache flash clear */
-case 0x4c: /* breakpoint action */
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
{
@@ -2328,6 +2338,18 @@ void helper_st_asi(target_ulong addr, uint64_t
val, int asi, int size)
env->mmuregs[reg]);
}
break;
+case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
+env->mmubpctrv = val & 0x;
+break;
+case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
+env->mmubpctrc = val & 0x3;
+break;
+case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
+env->mmubpctrs = val & 0x3;
+break;
+case 0x4c: /* SuperSPARC MMU Breakpoint Action */
+env->mmubpaction = val & 0x1fff;
+break;
case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
default:
--
1.6.2.4
From 52463bf611b3353842525cf7544d7b3d55da8a1e Mon Sep 17 00:00:00 2001
Message-Id: <52463bf611b3353842525cf7544d7b3d55da8a1e.1308433438.git.blauwir...@gmail.com>
From: Blue Swirl
Date: Sat, 18 Jun 2011 20:27:05 +
Subject: [PATCH] Sparc32: dummy implementation of MXCC MMU breakpoint registers
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints.
Signed-off-by: Blue Swirl
---
target-sparc/cpu.h |1 +
target-sparc/op_helper.c | 26 --
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 320530e..b5d5291 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -403,6 +403,7 @@ typedef struct CPUSPARCState {
uint32_t mmuregs[32];
uint64_t mxccdata[4];
uint64_t mxccregs[8];
+uint32_t mmubpctrv, mmubpctrc, mmubpctrs, mmubpaction;
uint64_t mmubpregs[4];
uint64_t prom_addr;
#endif
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index b38691e..e9cc1f5 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -1940,7 +1940,6 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
case 0x31: // Turbosparc RAM snoop
case 0x32: // Turbosparc page table descriptor diagnostic
case 0x39: /* data cache diagnostic register */
-case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
ret = 0;
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
@@ -1966,6 +1965,18 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
ret);
}
break;
+case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
+ret = env->mmubpctrv;
+break;
+case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
+ret = env->mmubpctrc;
+break;
+case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
+ret = env->mmubpctrs;
+break;
+case 0x4c: /* SuperS
