[Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt
The latest glibc provides a memrchr routine using an extended opcode of the 'dcbt' instruction : 000a7cc0 memrchr: a7cc0: 11 00 4c 3c addis r2,r12,17 a7cc4: b8 f8 42 38 addir2,r2,-1864 a7cc8: 14 2a e3 7c add r7,r3,r5 a7ccc: d0 00 07 7c neg r0,r7 a7cd0: ff ff e7 38 addir7,r7,-1 a7cd4: 78 1b 6a 7c mr r10,r3 a7cd8: 24 06 e6 78 rldicr r6,r7,0,56 a7cdc: 60 00 20 39 li r9,96 a7ce0: 2c 32 09 7e dcbtt r9,r6 which breaks grep, and other commands, in TCG mode : invalid bits: 0200 for opcode: 1f - 16 - 08 (7e09322c) 3fff799feca0 This patch adds the extended opcodes as no-ops just like the 'dcbt' instruction. Other 'dcb*' instructions might be impacted but they have not showed up yet. Signed-off-by: Cédric Le Goater c...@fr.ibm.com --- target-ppc/translate.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 951f15e055d4..431358a83ac3 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9596,7 +9596,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x0001, PPC_MISC), GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C1, PPC_CACHE), GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E1, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E1, PPC_CACHE), -GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0201, PPC_CACHE), +GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0001, PPC_CACHE), GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x0201, PPC_CACHE), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C1, PPC_CACHE_DCBZ), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x0181, PPC_ALTIVEC), -- 1.7.10.4
Re: [Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt
On 02/20/2014 02:07 PM, Alexander Graf wrote: On 20.02.2014, at 14:01, Cédric Le Goater c...@fr.ibm.com wrote: The latest glibc provides a memrchr routine using an extended opcode of the 'dcbt' instruction : 000a7cc0 memrchr: a7cc0: 11 00 4c 3c addis r2,r12,17 a7cc4: b8 f8 42 38 addir2,r2,-1864 a7cc8: 14 2a e3 7c add r7,r3,r5 a7ccc: d0 00 07 7c neg r0,r7 a7cd0: ff ff e7 38 addir7,r7,-1 a7cd4: 78 1b 6a 7c mr r10,r3 a7cd8: 24 06 e6 78 rldicr r6,r7,0,56 a7cdc: 60 00 20 39 li r9,96 a7ce0: 2c 32 09 7e dcbtt r9,r6 which breaks grep, and other commands, in TCG mode : invalid bits: 0200 for opcode: 1f - 16 - 08 (7e09322c) 3fff799feca0 This patch adds the extended opcodes as no-ops just like the 'dcbt' instruction. Other 'dcb*' instructions might be impacted but they have not showed up yet. Signed-off-by: Cédric Le Goater c...@fr.ibm.com Please also remove the 0x02 bit from dcbtst. I don't see anything in 2.07 indicating that that bit should be reserved and I prefer to have those two instructions be consistent with each other. ok. I will send a v2. Thanks, C.
Re: [Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt
On 20.02.2014, at 14:01, Cédric Le Goater c...@fr.ibm.com wrote: The latest glibc provides a memrchr routine using an extended opcode of the 'dcbt' instruction : 000a7cc0 memrchr: a7cc0: 11 00 4c 3c addis r2,r12,17 a7cc4: b8 f8 42 38 addir2,r2,-1864 a7cc8: 14 2a e3 7c add r7,r3,r5 a7ccc: d0 00 07 7c neg r0,r7 a7cd0: ff ff e7 38 addir7,r7,-1 a7cd4: 78 1b 6a 7c mr r10,r3 a7cd8: 24 06 e6 78 rldicr r6,r7,0,56 a7cdc: 60 00 20 39 li r9,96 a7ce0: 2c 32 09 7e dcbtt r9,r6 which breaks grep, and other commands, in TCG mode : invalid bits: 0200 for opcode: 1f - 16 - 08 (7e09322c) 3fff799feca0 This patch adds the extended opcodes as no-ops just like the 'dcbt' instruction. Other 'dcb*' instructions might be impacted but they have not showed up yet. Signed-off-by: Cédric Le Goater c...@fr.ibm.com Please also remove the 0x02 bit from dcbtst. I don't see anything in 2.07 indicating that that bit should be reserved and I prefer to have those two instructions be consistent with each other. Alex --- target-ppc/translate.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 951f15e055d4..431358a83ac3 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9596,7 +9596,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x0001, PPC_MISC), GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C1, PPC_CACHE), GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E1, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E1, PPC_CACHE), -GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0201, PPC_CACHE), +GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0001, PPC_CACHE), GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x0201, PPC_CACHE), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C1, PPC_CACHE_DCBZ), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x0181, PPC_ALTIVEC), -- 1.7.10.4
