Re: [Qemu-devel] [PATCH 0/3] MIPS64 user mode emulation in QEMU
Am 08.12.2011 06:25, schrieb kha...@kics.edu.pk: From: Khansa Butt kha...@kics.edu.pk This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt from HPCN Lab KICS UET Lahore. In previous patch set we were including Cavium specific instructions along with Cavium specifc registers in UME. Because of these register fields we had to bump the cpu version up but I noticed that cpu_save() and cpu_load() are not called in UME so we decided to postpone Octeon specific changes ( registers and instructions) and will include them in our SME work( we are currently working on system mode emulation of Octeon board) so we closing the following thread http://lists.gnu.org/archive/html/qemu-devel/2011-10/msg02665.html Please review this new patch set which is without cavium instruction support. I really hate to repeat myself... We receive lots of patches per day, so please make your patches easy to read, easy to understand and easy to review. If you check qemu-devel or the archives, you'll find many good examples that get committed - most people get this right on second try. Please don't ignore our comments from previous series: You previously sent a v3 series, now there's two unversioned series again. These should be v4 and v5 and should ALWAYS include a bulleted change log since initial version. This is to tell apart which is the latest series and which is superseded. v4 should include something like: Changes since v3 (or short v3 - v4): * Drop CPU load/save from series v2 - v3: ... v1 - v2: ... If v5 changed nothing but the cover letter, there would be no need to resend it, explanations for us can be added as a normal email reply. If you're missing feedback, best just reply to your cover letter with Ping? so that we have a chance of reviewing the email thread with previous comments. More in the individual patches. Andreas configure |1 + default-configs/mips64-linux-user.mak |1 + linux-user/main.c | 21 ++- linux-user/mips64/syscall.h |2 + linux-user/signal.c | 429 - target-mips/translate.c |4 + 6 files changed, 444 insertions(+), 14 deletions(-) create mode 100644 default-configs/mips64-linux-user.mak
[Qemu-devel] [PATCH 0/3] MIPS64 user mode emulation in QEMU
From: Khansa Butt kha...@kics.edu.pk This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt from HPCN Lab KICS UET Lahore. In previous patch set we were including Cavium specific instructions along with Cavium specifc registers in UME. Because of these register fields we had to bump the cpu version up but I noticed that cpu_save() and cpu_load() are not called in UME so we decided to postpone Octeon specific changes ( registers and instructions) and will include them in our SME work( we are currently working on system mode emulation of Octeon board) so we closing the following thread http://lists.gnu.org/archive/html/qemu-devel/2011-10/msg02665.html Please review this new patch set which is without cavium instruction support. configure |1 + default-configs/mips64-linux-user.mak |1 + linux-user/main.c | 21 ++- linux-user/mips64/syscall.h |2 + linux-user/signal.c | 429 - target-mips/translate.c |4 + 6 files changed, 444 insertions(+), 14 deletions(-) create mode 100644 default-configs/mips64-linux-user.mak -- 1.7.3.4
[Qemu-devel] [PATCH 0/3] MIPS64 user mode emulation in QEMU with Cavium specific instruction support
From: Khansa Butt kha...@kics.edu.pk This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt from HPCN Lab KICS UET Lahore. configure |1 + default-configs/mips64-linux-user.mak |1 + linux-user/main.c | 21 ++- linux-user/mips64/syscall.h |2 + linux-user/signal.c | 429 - target-mips/translate.c |4 + 6 files changed, 444 insertions(+), 14 deletions(-) create mode 100644 default-configs/mips64-linux-user.mak -- 1.7.3.4
Re: [Qemu-devel] [PATCH 0/3] MIPS64 user mode emulation in QEMU with Cavium specific instruction support
On 30 November 2011 11:07, kha...@kics.edu.pk wrote: From: Khansa Butt kha...@kics.edu.pk This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt from HPCN Lab KICS UET Lahore. This cover letter should say: * which version of this patch set this is (we've had multiple rounds of it) * what the changes are since previous versions If you don't make patchsets easy to review and re-review then people are less likely to do it. -- PMM
Re: [Qemu-devel] [PATCH 0/3] MIPS64 user mode emulation in QEMU with Cavium specific instruction support
This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt from HPCN Lab KICS UET Lahore. Shouldn't 'Signed-off-by' lines for mentioned persons be present in the relevant patches if this is a team work? -- Thanks. -- Max
Re: [Qemu-devel] [PATCH 0/3] MIPS64 user mode emulation in QEMU with Cavium specific instruction support
Hi, On 07/12/2011 02:09 PM, Khansa Butt wrote: We have developed Mips64 user mode emulation. In addition we implemented Cavium specific instruction along with octeon CPU definition. We need your support to make our contribution public ally available via making it open source. I tried to resolve the issues pointed out by Aurelien Jarno, Riku, Nathan and other friends and send the patches on Jul 5. Please review the patch series and give your feedback in the form of comments and suggestions I can only comment on the 1/3 part which touches linux-user code. I would prefer not change linux-user/signal.c just for changing code comment, but the rest of patch seems ok. However, the patch depends on changes in 2/3, so I can't apply it without the rest patches already included upstream by the target-mips maintainer. Riku
Re: [Qemu-devel] [PATCH 0/3] MIPS64 user mode emulation in QEMU with Cavium specific instruction support
Hi We have developed Mips64 user mode emulation. In addition we implemented Cavium specific instruction along with octeon CPU definition. We need your support to make our contribution public ally available via making it open source. I tried to resolve the issues pointed out by Aurelien Jarno, Riku, Nathan and other friends and send the patches on Jul 5. Please review the patch series and give your feedback in the form of comments and suggestions Thanks On Tue, Jul 5, 2011 at 2:19 PM, kha...@kics.edu.pk wrote: From: Khansa Butt kha...@kics.edu.pk This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt from HPCN Lab KICS UET Lahore. Cavium Networks's Octeon processors are based on MIPS64r2 We have Implemented 27 user mode Cavium specific instructions. Richard Henderson told me that QEMU does not support 64-bit address spaces in user mode from a 32-bit host. so this code will work only on 64 bit host. Although we did some workaround to run MIPS64 on 32 x86 and it can be generlized for other architectures. We will submit that after this submission. This development work is tested for 64 bit X86 and working fine all Cavium specific instructions are also tested. teast cases can be provided if required. Octeon binaries (ELF) can be downloaded from below links 1)http://dl.dropbox.com/u/19530066/hw_mips 2)http://dl.dropbox.com/u/19530066/matmul If you have any objection regarding the Implementation of Cavium instructions please read following notes. Notes * The detail of some instructions are as follows 1)seq rd,rs,rt seq--rd = 1 if rs = rt is equivalent to xor rd,rs,rt sltiu rd,rd,1 2)exts rt,rs,p,lenm1 rt = sign-extend(rsp+lenm1:p,lenm1) From reference manual of Cavium Networks Bit locations p + lenm1 to p are extracted from rs and the result is written into the lowest bits of destination register rt. The remaining bits in rt are a sign-extension of the most-significant bit of the bit field (i.e. rt63:lenm1 are all duplicates of the source-register bit rsp+lenm1). so we can't use any of 8,16 or 32 bit sign extention tcg function. To sign extend according to msb of bit field we have our own implementation 3)dmul rd,rs,rt This instruction is included in gen_arith() because it is three operand double word multiply instruction. -- 1.7.3.4
[Qemu-devel] [PATCH 0/3] MIPS64 user mode emulation in QEMU with Cavium specific instruction support
From: Khansa Butt kha...@kics.edu.pk This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt from HPCN Lab KICS UET Lahore. Cavium Networks's Octeon processors are based on MIPS64r2 We have Implemented 27 user mode Cavium specific instructions. Richard Henderson told me that QEMU does not support 64-bit address spaces in user mode from a 32-bit host. so this code will work only on 64 bit host. Although we did some workaround to run MIPS64 on 32 x86 and it can be generlized for other architectures. We will submit that after this submission. This development work is tested for 64 bit X86 and working fine all Cavium specific instructions are also tested. teast cases can be provided if required. Octeon binaries (ELF) can be downloaded from below links 1)http://dl.dropbox.com/u/19530066/hw_mips 2)http://dl.dropbox.com/u/19530066/matmul If you have any objection regarding the Implementation of Cavium instructions please read following notes. Notes * The detail of some instructions are as follows 1)seq rd,rs,rt seq--rd = 1 if rs = rt is equivalent to xor rd,rs,rt sltiu rd,rd,1 2)exts rt,rs,p,lenm1 rt = sign-extend(rsp+lenm1:p,lenm1) From reference manual of Cavium Networks Bit locations p + lenm1 to p are extracted from rs and the result is written into the lowest bits of destination register rt. The remaining bits in rt are a sign-extension of the most-significant bit of the bit field (i.e. rt63:lenm1 are all duplicates of the source-register bit rsp+lenm1). so we can't use any of 8,16 or 32 bit sign extention tcg function. To sign extend according to msb of bit field we have our own implementation 3)dmul rd,rs,rt This instruction is included in gen_arith() because it is three operand double word multiply instruction. -- 1.7.3.4
