[Qemu-devel] [PATCH 0/6] tcg sparc improvements

[Richard Henderson]

Three of these patches are related to the new instructions added
in 2011 with the VIS3 instruction set, as present in the T4 cpus.


r~


Richard Henderson (6):
  tcg-sparc: Support addsub2_i64
  tcg-sparc: Use ADDXC in addsub2_i64
  tcg-sparc: Fix setcond_i32 uninitialized value
  tcg-sparc: Use ADDXC in setcond_i64
  tcg-sparc: Rename ADDX/SUBX insns
  tcg-sparc: Use UMULXHI instruction

 disas/sparc.c  |  34 ++---
 include/elf.h  |  37 +++---
 tcg/sparc/tcg-target.c | 129 +++--
 tcg/sparc/tcg-target.h |  12 +++--
 4 files changed, 167 insertions(+), 45 deletions(-)

-- 
1.9.3

[Qemu-devel] [PATCH 0/6] tcg-sparc improvements

[Richard Henderson]

All of these patches are toward reducing the number of TCG opcodes
generated.  Three of the patches reduce the number of real insns
generated as well.  The ANDC and ORC opcodes are already generated
by the ARM, PPC, and Alpha translators.

I now have remote access to a real debian sparc64 machine, so this
has actually been tested on real hardware for a change.  ;-)


r~


Richard Henderson (6):
  tcg-sparc: Implement neg.
  tcg-sparc: Implement not.
  tcg: Optional target implementation of ANDC.
  tcg: Optional target implementation of ORC.
  tcg-sparc: Implement ANDC.
  tcg-sparc: Implement ORC.

 tcg/sparc/tcg-target.c |   30 ++
 tcg/sparc/tcg-target.h |   11 +--
 tcg/tcg-op.h   |   22 ++
 tcg/tcg-opc.h  |   12 
 4 files changed, 73 insertions(+), 2 deletions(-)

[Qemu-devel] [PATCH 0/6] tcg sparc improvements

[Richard Henderson]

Here's a split up version of the patch you looked at yesterday.


r~


Richard Henderson (6):
  tcg-sparc: Fix imm13 check in movi.
  tcg-sparc: Improve tcg_out_movi for sparc64.
  tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.
  tcg: Add tcg_unsigned_cond.
  tcg-sparc: Implement brcond2.
  tcg-sparc: Implement setcond, movcond, setcond2.

 tcg/sparc/tcg-target.c |  397 ++-
 tcg/tcg.h  |5 +
 2 files changed, 359 insertions(+), 43 deletions(-)