Re: [Qemu-devel] [PATCH 01/11] target/mips: Rename ASE_MMI to ASE_TOSHIBA_MMI, with Toshiba namespace

[Aleksandar Markovic]

> From: Fredrik Noring 
> Subject: [PATCH 01/11] target/mips: Rename ASE_MMI to ASE_TOSHIBA_MMI, with 
> Toshiba namespace
> 
> Several vendors have multimedia instruction (MMI) sets and other
> extensions of various kinds. ASE vendor namespaces make it clear these
> are not generic architectural features and also avoid name clashes.

ASE_XXX flags are not meant to identify a CPU or vendor. They are not wired to 
any configuration bit or CPU model. They are purely QEMU internal constructs, 
whose purpose was to make internal QEMU MIPS-specific code organization easier. 
In this case, ASE_MMI is an umbrella for all MMI-like ASEs, introduced with 
intent to make encapsulation of MMI-specific code better and easier. 
Differences between CPUs should be resolved by other means. Name 'ASE_MMI' is 
fine.

Thanks,
Aleksandar

[Qemu-devel] [PATCH 01/11] target/mips: Rename ASE_MMI to ASE_TOSHIBA_MMI, with Toshiba namespace

[Fredrik Noring]

Several vendors have multimedia instruction (MMI) sets and other
extensions of various kinds. ASE vendor namespaces make it clear these
are not generic architectural features and also avoid name clashes.

Reported-by: Maciej W. Rozycki 
Signed-off-by: Fredrik Noring 
---
 target/mips/mips-defs.h  | 2 +-
 target/mips/translate.c  | 3 ++-
 target/mips/translate_init.inc.c | 2 +-
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 5177618615..30b07e0bde 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -68,7 +68,7 @@
 /*
  *   bits 56-63: vendor-specific ASEs
  */
-#define ASE_MMI   0x0100ULL
+#define ASE_TOSHIBA_MMI   0x0100ULL
 
 /* MIPS CPU defines. */
 #defineCPU_MIPS1   (ISA_MIPS1)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c44a751be9..8547a6e6f6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -26092,7 +26092,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext 
*ctx)
 decode_opc_special(env, ctx);
 break;
 case OPC_SPECIAL2:
-if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
+if ((ctx->insn_flags & INSN_R5900) &&
+(ctx->insn_flags & ASE_TOSHIBA_MMI)) {
 decode_tx79_mmi(env, ctx);
 } else {
 decode_opc_special2_legacy(env, ctx);
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index 85da4a269c..5cd968366b 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -466,7 +466,7 @@ const mips_def_t mips_defs[] =
 #endif /* !CONFIG_USER_ONLY */
 .SEGBITS = 32,
 .PABITS = 32,
-.insn_flags = CPU_R5900 | ASE_MMI,
+.insn_flags = CPU_R5900 | ASE_TOSHIBA_MMI,
 .mmu_type = MMU_TYPE_R4000,
 },
 {
-- 
2.18.1