subject:"\[Qemu\-devel\] \[PATCH 03\/13\] target\-ppc\: implement lxvl instruction"

Re: [Qemu-devel] [PATCH 03/13] target-ppc: implement lxvl instruction

2016-12-06 Thread Nikunj A Dadhania

Richard Henderson  writes:
>> +void helper_lxvl(CPUPPCState *env, target_ulong addr,
>> + target_ulong xt_num, target_ulong rb)
>> +{
>> +ppc_vsr_t xt;
>> +
>> +getVSR(xt_num, &xt, env);
>> +if (unlikely((rb & 0xFF) == 0)) {
>> +xt.s128 = int128_make128(0, 0);
>> +} else {
>> +target_ulong end = ((rb & 0xFF) * 8) - 1;

Found the above wrong it the code, ISA is extracting bit 0:7
from GPR[RB]

Regards
Nikunj

Re: [Qemu-devel] [PATCH 03/13] target-ppc: implement lxvl instruction

2016-12-05 Thread Nikunj A Dadhania

Richard Henderson  writes:

> On 12/05/2016 03:25 AM, Nikunj A Dadhania wrote:
>> lxvl: Load VSX Vector with Length
>> 
>> Little/Big-endian Storage:
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>> 
>> Loading 14 bytes results in:
>> 
>> Vector (8-bit elements) in BE:
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>> 
>> Vector (8-bit elements) in LE:
>> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
>> |00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
>> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
>> 
>> Signed-off-by: Nikunj A Dadhania 
>> ---
>>  target-ppc/helper.h |  1 +
>>  target-ppc/mem_helper.c | 25 +
>>  target-ppc/translate/vsx-impl.inc.c | 27 +++
>>  target-ppc/translate/vsx-ops.inc.c  |  1 +
>>  4 files changed, 54 insertions(+)
>> 
>> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
>> index bc39efb..d9ccafd 100644
>> --- a/target-ppc/helper.h
>> +++ b/target-ppc/helper.h
>> @@ -317,6 +317,7 @@ DEF_HELPER_3(lvewx, void, env, avr, tl)
>>  DEF_HELPER_3(stvebx, void, env, avr, tl)
>>  DEF_HELPER_3(stvehx, void, env, avr, tl)
>>  DEF_HELPER_3(stvewx, void, env, avr, tl)
>> +DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
>>  DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
>>  DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
>>  DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
>> diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
>> index 1ab8a6e..0a8ff54 100644
>> --- a/target-ppc/mem_helper.c
>> +++ b/target-ppc/mem_helper.c
>> @@ -24,6 +24,7 @@
>>  
>>  #include "helper_regs.h"
>>  #include "exec/cpu_ldst.h"
>> +#include "internal.h"
>>  
>>  //#define DEBUG_OP
>>  
>> @@ -284,6 +285,30 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
>>  #undef I
>>  #undef LVE
>>  
>> +void helper_lxvl(CPUPPCState *env, target_ulong addr,
>> + target_ulong xt_num, target_ulong rb)
>> +{
>> +ppc_vsr_t xt;
>> +
>> +getVSR(xt_num, &xt, env);
>> +if (unlikely((rb & 0xFF) == 0)) {
>> +xt.s128 = int128_make128(0, 0);
>> +} else {
>> +target_ulong end = ((rb & 0xFF) * 8) - 1;
>> +if (msr_le) {
>> +xt.u64[HI_IDX] = bswap64(cpu_ldq_data_ra(env, addr, GETPC()));
>> +addr = addr_add(env, addr, 8);
>> +xt.u64[LO_IDX] = bswap64(cpu_ldq_data_ra(env, addr, GETPC()));
>
> hi/lo assignment reversed for le.

Already taken care here:

#if defined(HOST_WORDS_BIGENDIAN)
#define HI_IDX 0
#define LO_IDX 1
#else
#define HI_IDX 1
#define LO_IDX 0
#endif

>
>> +} else {
>> +xt.u64[HI_IDX] = cpu_ldq_data_ra(env, addr, GETPC());
>> +addr = addr_add(env, addr, 8);
>> +xt.u64[LO_IDX] = cpu_ldq_data_ra(env, addr, GETPC());
>> +}
>> +xt.s128 = int128_and(xt.s128, mask_u128(0, end));
>
> I don't think mask_u128 does the right thing for end > 127.
> I think you need a check here.

Sure. Will do that.

Regards
Nikunj

Re: [Qemu-devel] [PATCH 03/13] target-ppc: implement lxvl instruction

2016-12-05 Thread Richard Henderson

On 12/05/2016 03:25 AM, Nikunj A Dadhania wrote:
> lxvl: Load VSX Vector with Length
> 
> Little/Big-endian Storage:
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
> 
> Loading 14 bytes results in:
> 
> Vector (8-bit elements) in BE:
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
> 
> Vector (8-bit elements) in LE:
> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
> |00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
> 
> Signed-off-by: Nikunj A Dadhania 
> ---
>  target-ppc/helper.h |  1 +
>  target-ppc/mem_helper.c | 25 +
>  target-ppc/translate/vsx-impl.inc.c | 27 +++
>  target-ppc/translate/vsx-ops.inc.c  |  1 +
>  4 files changed, 54 insertions(+)
> 
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index bc39efb..d9ccafd 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -317,6 +317,7 @@ DEF_HELPER_3(lvewx, void, env, avr, tl)
>  DEF_HELPER_3(stvebx, void, env, avr, tl)
>  DEF_HELPER_3(stvehx, void, env, avr, tl)
>  DEF_HELPER_3(stvewx, void, env, avr, tl)
> +DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
>  DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
>  DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
>  DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
> diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
> index 1ab8a6e..0a8ff54 100644
> --- a/target-ppc/mem_helper.c
> +++ b/target-ppc/mem_helper.c
> @@ -24,6 +24,7 @@
>  
>  #include "helper_regs.h"
>  #include "exec/cpu_ldst.h"
> +#include "internal.h"
>  
>  //#define DEBUG_OP
>  
> @@ -284,6 +285,30 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
>  #undef I
>  #undef LVE
>  
> +void helper_lxvl(CPUPPCState *env, target_ulong addr,
> + target_ulong xt_num, target_ulong rb)
> +{
> +ppc_vsr_t xt;
> +
> +getVSR(xt_num, &xt, env);
> +if (unlikely((rb & 0xFF) == 0)) {
> +xt.s128 = int128_make128(0, 0);
> +} else {
> +target_ulong end = ((rb & 0xFF) * 8) - 1;
> +if (msr_le) {
> +xt.u64[HI_IDX] = bswap64(cpu_ldq_data_ra(env, addr, GETPC()));
> +addr = addr_add(env, addr, 8);
> +xt.u64[LO_IDX] = bswap64(cpu_ldq_data_ra(env, addr, GETPC()));

hi/lo assignment reversed for le.

> +} else {
> +xt.u64[HI_IDX] = cpu_ldq_data_ra(env, addr, GETPC());
> +addr = addr_add(env, addr, 8);
> +xt.u64[LO_IDX] = cpu_ldq_data_ra(env, addr, GETPC());
> +}
> +xt.s128 = int128_and(xt.s128, mask_u128(0, end));

I don't think mask_u128 does the right thing for end > 127.
I think you need a check here.


r~

[Qemu-devel] [PATCH 03/13] target-ppc: implement lxvl instruction

2016-12-05 Thread Nikunj A Dadhania

lxvl: Load VSX Vector with Length

Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+

Loading 14 bytes results in:

Vector (8-bit elements) in BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+

Vector (8-bit elements) in LE:
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

Signed-off-by: Nikunj A Dadhania 
---
 target-ppc/helper.h |  1 +
 target-ppc/mem_helper.c | 25 +
 target-ppc/translate/vsx-impl.inc.c | 27 +++
 target-ppc/translate/vsx-ops.inc.c  |  1 +
 4 files changed, 54 insertions(+)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index bc39efb..d9ccafd 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -317,6 +317,7 @@ DEF_HELPER_3(lvewx, void, env, avr, tl)
 DEF_HELPER_3(stvebx, void, env, avr, tl)
 DEF_HELPER_3(stvehx, void, env, avr, tl)
 DEF_HELPER_3(stvewx, void, env, avr, tl)
+DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
 DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
 DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
 DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index 1ab8a6e..0a8ff54 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -24,6 +24,7 @@
 
 #include "helper_regs.h"
 #include "exec/cpu_ldst.h"
+#include "internal.h"
 
 //#define DEBUG_OP
 
@@ -284,6 +285,30 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
 #undef I
 #undef LVE
 
+void helper_lxvl(CPUPPCState *env, target_ulong addr,
+ target_ulong xt_num, target_ulong rb)
+{
+ppc_vsr_t xt;
+
+getVSR(xt_num, &xt, env);
+if (unlikely((rb & 0xFF) == 0)) {
+xt.s128 = int128_make128(0, 0);
+} else {
+target_ulong end = ((rb & 0xFF) * 8) - 1;
+if (msr_le) {
+xt.u64[HI_IDX] = bswap64(cpu_ldq_data_ra(env, addr, GETPC()));
+addr = addr_add(env, addr, 8);
+xt.u64[LO_IDX] = bswap64(cpu_ldq_data_ra(env, addr, GETPC()));
+} else {
+xt.u64[HI_IDX] = cpu_ldq_data_ra(env, addr, GETPC());
+addr = addr_add(env, addr, 8);
+xt.u64[LO_IDX] = cpu_ldq_data_ra(env, addr, GETPC());
+}
+xt.s128 = int128_and(xt.s128, mask_u128(0, end));
+}
+putVSR(xt_num, &xt, env);
+}
+
 #undef HI_IDX
 #undef LO_IDX
 
diff --git a/target-ppc/translate/vsx-impl.inc.c 
b/target-ppc/translate/vsx-impl.inc.c
index 2fbdbd2..e53f91e 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -240,6 +240,33 @@ VSX_VECTOR_LOAD_STORE(stxv, st_i64, 0)
 VSX_VECTOR_LOAD_STORE(lxvx, ld_i64, 1)
 VSX_VECTOR_LOAD_STORE(stxvx, st_i64, 1)
 
+#define VSX_VECTOR_LOAD_STORE_LENGTH(name)  \
+static void gen_##name(DisasContext *ctx)   \
+{   \
+TCGv EA, xt;\
+\
+if (xT(ctx->opcode) < 32) { \
+if (unlikely(!ctx->vsx_enabled)) {  \
+gen_exception(ctx, POWERPC_EXCP_VSXU);  \
+return; \
+}   \
+} else {\
+if (unlikely(!ctx->altivec_enabled)) {  \
+gen_exception(ctx, POWERPC_EXCP_VPU);   \
+return; \
+}   \
+}   \
+EA = tcg_temp_new();\
+xt = tcg_const_tl(xT(ctx->opcode)); \
+gen_set_access_type(ctx, ACCESS_INT);   \
+gen_addr_register(ctx, EA); \
+gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
+tcg_temp_free(EA);  \
+tcg_temp_free(xt);  \
+}
+
+VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
+
 #define VSX_LOAD_SCALAR_DS(name, operation)   \
 static void gen_##name(DisasContext *ctx) \
 { \
diff --git a/target-ppc/translate/vsx-ops.inc.c 
b/target-ppc/translate/vsx-ops

Re: [Qemu-devel] [PATCH 03/13] target-ppc: implement lxvl instruction

Re: [Qemu-devel] [PATCH 03/13] target-ppc: implement lxvl instruction

Re: [Qemu-devel] [PATCH 03/13] target-ppc: implement lxvl instruction

[Qemu-devel] [PATCH 03/13] target-ppc: implement lxvl instruction

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