Re: [Qemu-devel] [PATCH 04/28] target/riscv: Convert RVXI arithmetic insns to decodetree
On Fri, 19 Oct 2018 04:00:33 PDT (-0700), kbast...@mail.uni-paderborn.de wrote:
Hi Richard,
On 10/12/18 8:46 PM, Richard Henderson wrote:
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
+static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn)
+{
+gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
+return true;
+}
+static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn)
+{
+if (a->rd != 0) {
+TCGv t = tcg_temp_new();
+gen_get_gpr(t, a->rs1);
+
+if (a->shamt >= TARGET_LONG_BITS) {
+gen_exception_illegal(ctx);
+return true;
+}
+tcg_gen_shli_tl(t, t, a->shamt);
+
+gen_set_gpr(a->rd, t);
+tcg_temp_free(t);
+} /* NOP otherwise */
+return true;
+}
Spacing. Any reason why trans_slli (and the other shifts) aren't using
gen_arith_imm as well?
Their opcode is not uniquely defined in instmap.h, just a generic
OPC_RISC_SHIFT_RIGHT_IW. I guess I can give the opcode as a magic value
for now.
Shifts are the only arithmetic operations that aren't uniquely defined by func3
(the opcode), but instead have another bit packed in where the immediate
usually lives to differentiate between arithmetic and logical shifts. This
pretty much always ends up as a bit of a special case in software decoders.
Re: [Qemu-devel] [PATCH 04/28] target/riscv: Convert RVXI arithmetic insns to decodetree
Hi Richard,
On 10/12/18 8:46 PM, Richard Henderson wrote:
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
+static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn)
+{
+gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
+return true;
+}
+static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn)
+{
+if (a->rd != 0) {
+TCGv t = tcg_temp_new();
+gen_get_gpr(t, a->rs1);
+
+if (a->shamt >= TARGET_LONG_BITS) {
+gen_exception_illegal(ctx);
+return true;
+}
+tcg_gen_shli_tl(t, t, a->shamt);
+
+gen_set_gpr(a->rd, t);
+tcg_temp_free(t);
+} /* NOP otherwise */
+return true;
+}
Spacing. Any reason why trans_slli (and the other shifts) aren't using
gen_arith_imm as well?
Their opcode is not uniquely defined in instmap.h, just a generic
OPC_RISC_SHIFT_RIGHT_IW. I guess I can give the opcode as a magic value
for now.
Cheers,
Bastian
Re: [Qemu-devel] [PATCH 04/28] target/riscv: Convert RVXI arithmetic insns to decodetree
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn)
> +{
> +gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
> +return true;
> +}
> +static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn)
> +{
> +if (a->rd != 0) {
> +TCGv t = tcg_temp_new();
> +gen_get_gpr(t, a->rs1);
> +
> +if (a->shamt >= TARGET_LONG_BITS) {
> +gen_exception_illegal(ctx);
> +return true;
> +}
> +tcg_gen_shli_tl(t, t, a->shamt);
> +
> +gen_set_gpr(a->rd, t);
> +tcg_temp_free(t);
> +} /* NOP otherwise */
> +return true;
> +}
Spacing. Any reason why trans_slli (and the other shifts) aren't using
gen_arith_imm as well?
> +static bool trans_addw(DisasContext *ctx, arg_addw *a, uint32_t insn)
> +{
> +#if !defined(TARGET_RISCV64)
> +gen_exception_illegal(ctx);
> +return true;
> +#endif
> +gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
> +return true;
> +}
return false, like you did for trans_ld?
r~
[Qemu-devel] [PATCH 04/28] target/riscv: Convert RVXI arithmetic insns to decodetree
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 36
target/riscv/insn_trans/trans_rvi.inc.c | 221
target/riscv/translate.c| 9 -
3 files changed, 257 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index badd1d9216..cb7622e223 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -21,6 +21,9 @@
%rs1 15:5
%rd7:5
+%sh620:6
+%sh520:5
+
# immediates:
%imm_i20:s12
%imm_s25:s7 7:5
@@ -30,14 +33,19 @@
# Argument sets:
&branchimm rs2 rs1
+&shift shamt rs1 rd
# Formats 32:
+@r ... . . ... . ... %rs2 %rs1
%rd
@i . ... . ... imm=%imm_i %rs1
%rd
@b ... . . ... . ... &branch imm=%imm_b %rs2 %rs1
@s ... . . ... . ... imm=%imm_s %rs2 %rs1
@u . ... imm=%imm_u
%rd
@j . ... imm=%imm_j
%rd
+@sh6 .. .. . ... . ... &shift shamt=%sh6 %rs1
%rd
+@sh5 ... . . ... . ... &shift shamt=%sh5 %rs1
%rd
+
# *** RV32I Base Instruction Set ***
lui . 0110111 @u
auipc . 0010111 @u
@@ -57,8 +65,36 @@ lhu . 101 . 011 @i
sb ... . . 000 . 0100011 @s
sh ... . . 001 . 0100011 @s
sw ... . . 010 . 0100011 @s
+addi . 000 . 0010011 @i
+slti . 010 . 0010011 @i
+sltiu . 011 . 0010011 @i
+xori . 100 . 0010011 @i
+ori . 110 . 0010011 @i
+andi . 111 . 0010011 @i
+slli 00 ... 001 . 0010011 @sh6
+srli 00 ... 101 . 0010011 @sh6
+srai 01 ... 101 . 0010011 @sh6
+add 000 .. 000 . 0110011 @r
+sub 010 .. 000 . 0110011 @r
+sll 000 .. 001 . 0110011 @r
+slt 000 .. 010 . 0110011 @r
+sltu 000 .. 011 . 0110011 @r
+xor 000 .. 100 . 0110011 @r
+srl 000 .. 101 . 0110011 @r
+sra 010 .. 101 . 0110011 @r
+or 000 .. 110 . 0110011 @r
+and 000 .. 111 . 0110011 @r
# *** RV64I Base Instruction Set (in addition to RV32I) ***
lwu . 110 . 011 @i
ld . 011 . 011 @i
sd ... . . 011 . 0100011 @s
+addiw . 000 . 0011011 @i
+slliw000 . . 001 . 0011011 @sh5
+srliw000 . . 101 . 0011011 @sh5
+sraiw010 . . 101 . 0011011 @sh5
+addw 000 . . 000 . 0111011 @r
+subw 010 . . 000 . 0111011 @r
+sllw 000 . . 001 . 0111011 @r
+srlw 000 . . 101 . 0111011 @r
+sraw 010 . . 101 . 0111011 @r
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 5803518fdc..2b017cf4a4 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -156,3 +156,224 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a,
uint32_t insn)
return false;
#endif
}
+
+static bool trans_addi(DisasContext *ctx, arg_addi *a, uint32_t insn)
+{
+gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_slti(DisasContext *ctx, arg_slti *a, uint32_t insn)
+{
+gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a, uint32_t insn)
+{
+gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
+return true;
+}
+
+static bool trans_xori(DisasContext *ctx, arg_xori *a, uint32_t insn)
+{
+gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
+return true;
+}
+static bool trans_ori(DisasContext *ctx, arg_ori *a, uint32_t insn)
+{
+gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm);
+return true;
+}
+static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn)
+{
+gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
+return true;
+}
+static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn)
+{
+if (a->rd != 0) {
+TCGv
