The Application Interrupt and Reset Control Register has some changes
for v8M:
* new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have
real state if the security extension is implemented and otherwise
are constant
* the PRIGROUP field is banked between security states
* non-secure code can be blocked from using the SYSRESET bit
to reset the system if SYSRESETREQS is set
Implement the new state and the changes to register read and write.
For the moment we ignore the effects of the secure PRIGROUP.
We will implement the effects of PRIS and BFHFNMIS later.
Signed-off-by: Peter Maydell
---
include/hw/intc/armv7m_nvic.h | 3 ++-
target/arm/cpu.h | 12 +++
hw/intc/armv7m_nvic.c | 49 +--
target/arm/cpu.c | 7 +++
4 files changed, 59 insertions(+), 12 deletions(-)
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 329774e..e96e488 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -55,7 +55,8 @@ typedef struct NVICState {
* Entries in sec_vectors[] for non-banked exception numbers are unused.
*/
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
-uint32_t prigroup;
+/* The PRIGROUP field in AIRCR is banked */
+uint32_t prigroup[M_REG_NUM_BANKS];
/* The following fields are all cached state that can be recalculated
* from the vectors[] and sec_vectors[] arrays and the prigroup field:
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5a1f957..7e661c8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -449,6 +449,7 @@ typedef struct CPUARMState {
int exception;
uint32_t primask[M_REG_NUM_BANKS];
uint32_t faultmask[M_REG_NUM_BANKS];
+uint32_t aircr; /* only holds r/w state if security extn implemented */
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
} v7m;
@@ -1200,6 +1201,17 @@ FIELD(V7M_CCR, STKALIGN, 9, 1)
FIELD(V7M_CCR, DC, 16, 1)
FIELD(V7M_CCR, IC, 17, 1)
+/* V7M AIRCR bits */
+FIELD(V7M_AIRCR, VECTRESET, 0, 1)
+FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
+FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
+FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
+FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
+FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
+FIELD(V7M_AIRCR, PRIS, 14, 1)
+FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
+FIELD(V7M_AIRCR, VECTKEY, 16, 16)
+
/* V7M CFSR bits for MMFSR */
FIELD(V7M_CFSR, IACCVIOL, 0, 1)
FIELD(V7M_CFSR, DACCVIOL, 1, 1)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 8388d64..585b1a7 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -129,7 +129,7 @@ static bool nvic_isrpending(NVICState *s)
*/
static inline uint32_t nvic_gprio_mask(NVICState *s)
{
-return ~0U << (s->prigroup + 1);
+return ~0U << (s->prigroup[M_REG_NS] + 1);
}
/* Recompute vectpending and exception_prio */
@@ -451,8 +451,21 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset,
MemTxAttrs attrs)
return val;
case 0xd08: /* Vector Table Offset. */
return cpu->env.v7m.vecbase[attrs.secure];
-case 0xd0c: /* Application Interrupt/Reset Control. */
-return 0xfa05 | (s->prigroup << 8);
+case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
+val = 0xfa05 | (s->prigroup[attrs.secure] << 8);
+if (attrs.secure) {
+/* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
+val |= cpu->env.v7m.aircr;
+} else {
+if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+/* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
+ * security isn't supported then BFHFNMINS is RAO (and
+ * the bit in env.v7m.aircr is always set).
+ */
+val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK;
+}
+}
+return val;
case 0xd10: /* System Control. */
/* TODO: Implement SLEEPONEXIT. */
return 0;
@@ -660,22 +673,35 @@ static void nvic_writel(NVICState *s, uint32_t offset,
uint32_t value,
case 0xd08: /* Vector Table Offset. */
cpu->env.v7m.vecbase[attrs.secure] = value & 0xff80;
break;
-case 0xd0c: /* Application Interrupt/Reset Control. */
-if ((value >> 16) == 0x05fa) {
-if (value & 4) {
-qemu_irq_pulse(s->sysresetreq);
+case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
+if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) {
+if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
+if (attrs.secure ||
+!(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
+qemu_irq_pulse(s->sysresetreq);
+}
}
-if (value & 2) {
+if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
qemu_log_mask(LOG_GUEST_ERROR,
"Se