Re: [Qemu-devel] [PATCH 07/28] target/riscv: Convert RVXM insns to decodetree

[Richard Henderson]

On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann 
> Signed-off-by: Peer Adelt 
> ---
>  target/riscv/insn32.decode  | 17 +
>  target/riscv/insn_trans/trans_rvm.inc.c | 87 +
>  target/riscv/translate.c| 10 +--
>  3 files changed, 105 insertions(+), 9 deletions(-)
>  create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c


Reviewed-by: Richard Henderson 

> +}
> +static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn)

Spacing.


r~

[Qemu-devel] [PATCH 07/28] target/riscv: Convert RVXM insns to decodetree

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann 
Signed-off-by: Peer Adelt 
---
 target/riscv/insn32.decode  | 17 +
 target/riscv/insn_trans/trans_rvm.inc.c | 87 +
 target/riscv/translate.c| 10 +--
 3 files changed, 105 insertions(+), 9 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index dbb177395d..15dd6234a4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -114,3 +114,20 @@ subw 010 .  . 000 . 0111011 @r
 sllw 000 .  . 001 . 0111011 @r
 srlw 000 .  . 101 . 0111011 @r
 sraw 010 .  . 101 . 0111011 @r
+
+# *** RV32M Standard Extension ***
+mul  001 .  . 000 . 0110011 @r
+mulh 001 .  . 001 . 0110011 @r
+mulhsu   001 .  . 010 . 0110011 @r
+mulhu001 .  . 011 . 0110011 @r
+div  001 .  . 100 . 0110011 @r
+divu 001 .  . 101 . 0110011 @r
+rem  001 .  . 110 . 0110011 @r
+remu 001 .  . 111 . 0110011 @r
+
+# *** RV64M Standard Extension (in addition to RV32M) ***
+mulw 001 .  . 000 . 0111011 @r
+divw 001 .  . 100 . 0111011 @r
+divuw001 .  . 101 . 0111011 @r
+remw 001 .  . 110 . 0111011 @r
+remuw001 .  . 111 . 0111011 @r
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c 
b/target/riscv/insn_trans/trans_rvm.inc.c
new file mode 100644
index 00..2d0fd6a64f
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -0,0 +1,87 @@
+/*
+ * RISC-V translation routines for the RV64M Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.ad...@hni.uni-paderborn.de
+ *Bastian Koppelmann, kbast...@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+
+static bool trans_mul(DisasContext *ctx, arg_mul *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
+return true;
+}
+static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
+return true;
+}
+static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
+return true;
+}
+static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
+return true;
+}
+
+static bool trans_div(DisasContext *ctx, arg_div *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
+return true;
+}
+static bool trans_divu(DisasContext *ctx, arg_divu *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
+return true;
+}
+static bool trans_rem(DisasContext *ctx, arg_rem *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
+return true;
+}
+static bool trans_remu(DisasContext *ctx, arg_remu *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
+return true;
+}
+static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
+return true;
+}
+static bool trans_divw(DisasContext *ctx, arg_divw *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
+return true;
+}
+static bool trans_divuw(DisasContext *ctx, arg_divuw *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
+return true;
+}
+static bool trans_remw(DisasContext *ctx, arg_remw *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
+return true;
+}
+static bool trans_remuw(DisasContext *ctx, arg_remuw *a, uint32_t insn)
+{
+gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
+return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7438205492..7c1ecfaf1b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1638,6 +1638,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
 #include "decode_insn32.inc.c"
 /* Include insn module translation function */
 #includ