Re: [Qemu-devel] [PATCH 08/18] target/arm: support access to vector guest registers as globals

[Richard Henderson]

On 01/17/2017 01:07 AM, Kirill Batuzov wrote:

+for (i = 0; i < 16; i++) {
+overlap_temps[i][0] = GET_TCGV_V128(cpu_Q[i]);
+overlap_temps[i][1] = (TCGArg)-1;
+sub_temps[i][0] = GET_TCGV_V64(cpu_D[i * 2]);
+sub_temps[i][1] = GET_TCGV_V64(cpu_D[i * 2 + 1]);
+sub_temps[i][2] = (TCGArg)-1;
+tcg_temp_set_overlap_temps(GET_TCGV_V64(cpu_D[i * 2]),
+   overlap_temps[i]);
+tcg_temp_set_overlap_temps(GET_TCGV_V64(cpu_D[i * 2 + 1]),
+   overlap_temps[i]);
+tcg_temp_set_sub_temps(GET_TCGV_V128(cpu_Q[i]), sub_temps[i]);
 }


Should we simply detect this generically as the registers are declared?  This 
seems tedious to do for each target.



r~

[Qemu-devel] [PATCH 08/18] target/arm: support access to vector guest registers as globals

[Kirill Batuzov]

To support vector guest registers as globals we need to do two things:

1) create corresponding globals,
2) mark which globals can overlap,

Signed-off-by: Kirill Batuzov 
---

I've declared regnames for new globals the same way they used to be declared for
scalar regs. checkpatch complains about it. Should I move '{' to the same line
for all 3 arrays?

---
 target/arm/translate.c | 45 +++--
 1 file changed, 43 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0ad9070..2b81b5d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -65,6 +65,12 @@ static TCGv_i32 cpu_R[16];
 TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
 TCGv_i64 cpu_exclusive_addr;
 TCGv_i64 cpu_exclusive_val;
+static TCGv_v128 cpu_Q[16];
+static TCGv_v64 cpu_D[32];
+#ifdef CONFIG_USER_ONLY
+TCGv_i64 cpu_exclusive_test;
+TCGv_i32 cpu_exclusive_info;
+#endif
 
 /* FIXME:  These should be removed.  */
 static TCGv_i32 cpu_F0s, cpu_F1s;
@@ -72,14 +78,26 @@ static TCGv_i64 cpu_F0d, cpu_F1d;
 
 #include "exec/gen-icount.h"
 
-static const char *regnames[] =
+static const char *regnames_r[] =
 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
 
+static const char *regnames_q[] =
+{ "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
+  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" };
+
+static const char *regnames_d[] =
+{ "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
+  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
+  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31" };
+
 /* initialize TCG globals.  */
 void arm_translate_init(void)
 {
 int i;
+static TCGArg overlap_temps[16][2];
+static TCGArg sub_temps[16][3];
 
 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
 tcg_ctx.tcg_env = cpu_env;
@@ -87,7 +105,30 @@ void arm_translate_init(void)
 for (i = 0; i < 16; i++) {
 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
   offsetof(CPUARMState, regs[i]),
-  regnames[i]);
+  regnames_r[i]);
+}
+for (i = 0; i < 16; i++) {
+cpu_Q[i] = tcg_global_mem_new_v128(cpu_env,
+   offsetof(CPUARMState,
+vfp.regs[2 * i]),
+   regnames_q[i]);
+}
+for (i = 0; i < 32; i++) {
+cpu_D[i] = tcg_global_mem_new_v64(cpu_env,
+  offsetof(CPUARMState, vfp.regs[i]),
+  regnames_d[i]);
+}
+for (i = 0; i < 16; i++) {
+overlap_temps[i][0] = GET_TCGV_V128(cpu_Q[i]);
+overlap_temps[i][1] = (TCGArg)-1;
+sub_temps[i][0] = GET_TCGV_V64(cpu_D[i * 2]);
+sub_temps[i][1] = GET_TCGV_V64(cpu_D[i * 2 + 1]);
+sub_temps[i][2] = (TCGArg)-1;
+tcg_temp_set_overlap_temps(GET_TCGV_V64(cpu_D[i * 2]),
+   overlap_temps[i]);
+tcg_temp_set_overlap_temps(GET_TCGV_V64(cpu_D[i * 2 + 1]),
+   overlap_temps[i]);
+tcg_temp_set_sub_temps(GET_TCGV_V128(cpu_Q[i]), sub_temps[i]);
 }
 cpu_CF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, CF), "CF");
 cpu_NF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, NF), "NF");
-- 
2.1.4