[Qemu-devel] [PATCH 09/27] Use hash more consistently in ppc mmu code
Currently, get_segment() has a variable called hash. However it doesn't
(quite) get the hash value for the ppc hashed page table. Instead it
gets the hash shifted - effectively the offset of the hash bucket within
the hash page table.
As well, as being different to the normal use of plain hash in the
architecture documentation, this usage necessitates some awkward 32/64
dependent masks and shifts which clutter up the path in get_segment().
This patch alters the code to use raw hash values through get_segment()
including storing raw hashes instead of pte group offsets in the ctx
structure. This cleans up the path noticeably.
This does necessitate 32/64 dependent shifts when the hash values are
taken out of the ctx structure and used, but those paths already have
32/64 bit variants so this is less awkward than it was in get_segment().
Signed-off-by: David Gibson d...@au1.ibm.com
---
target-ppc/cpu.h|5 ++-
target-ppc/helper.c | 95 --
2 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ead4566..cee1057 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -367,6 +367,9 @@ union ppc_tlb_t {
#define SDR_64_HTABSIZE0x001FULL
#endif /* defined(TARGET_PPC64 */
+#define HASH_PTE_SIZE_32 8
+#define HASH_PTE_SIZE_64 16
+
typedef struct ppc_slb_t ppc_slb_t;
struct ppc_slb_t {
uint64_t esid;
@@ -744,7 +747,7 @@ struct mmu_ctx_t {
target_phys_addr_t raddr; /* Real address */
target_phys_addr_t eaddr; /* Effective address */
int prot; /* Protection bits */
-target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
+target_phys_addr_t hash[2];/* Pagetable hash values */
target_ulong ptem; /* Virtual segment ID | API */
int key; /* Access key*/
int nx;/* Non-execute area */
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 68d2d9c..0efa2a8 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -567,21 +567,30 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx,
target_ulong virtual,
return ret;
}
+static inline target_phys_addr_t get_pteg_offset(CPUState *env,
+ target_phys_addr_t hash,
+ int pte_size)
+{
+return (hash * pte_size * 8) env-htab_mask;
+}
+
/* PTE table lookup */
-static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
-int type, int target_page_bits)
+static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h,
+int rw, int type, int target_page_bits)
{
-target_ulong base, pte0, pte1;
+target_phys_addr_t pteg_off;
+target_ulong pte0, pte1;
int i, good = -1;
int ret, r;
ret = -1; /* No entry found */
-base = ctx-pg_addr[h];
+pteg_off = get_pteg_offset(env, ctx-hash[h],
+ is_64b ? HASH_PTE_SIZE_64 : HASH_PTE_SIZE_32);
for (i = 0; i 8; i++) {
#if defined(TARGET_PPC64)
if (is_64b) {
-pte0 = ldq_phys(base + (i * 16));
-pte1 = ldq_phys(base + (i * 16) + 8);
+pte0 = ldq_phys(env-htab_base + pteg_off + (i * 16));
+pte1 = ldq_phys(env-htab_base + pteg_off + (i * 16) + 8);
/* We have a TLB that saves 4K pages, so let's
* split a huge page to 4k chunks */
@@ -592,17 +601,17 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b,
int h, int rw,
r = pte64_check(ctx, pte0, pte1, h, rw, type);
LOG_MMU(Load pte from TARGET_FMT_lx = TARGET_FMT_lx
TARGET_FMT_lx %d %d %d TARGET_FMT_lx \n,
-base + (i * 16), pte0, pte1, (int)(pte0 1), h,
+pteg_base + (i * 16), pte0, pte1, (int)(pte0 1), h,
(int)((pte0 1) 1), ctx-ptem);
} else
#endif
{
-pte0 = ldl_phys(base + (i * 8));
-pte1 = ldl_phys(base + (i * 8) + 4);
+pte0 = ldl_phys(env-htab_base + pteg_off + (i * 8));
+pte1 = ldl_phys(env-htab_base + pteg_off + (i * 8) + 4);
r = pte32_check(ctx, pte0, pte1, h, rw, type);
LOG_MMU(Load pte from TARGET_FMT_lx = TARGET_FMT_lx
TARGET_FMT_lx %d %d %d TARGET_FMT_lx \n,
-base + (i * 8), pte0, pte1, (int)(pte0 31), h,
+pteg_base + (i * 8), pte0, pte1, (int)(pte0 31), h,
(int)((pte0 6) 1), ctx-ptem);
}
switch (r) {
@@ -638,11 +647,13 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b,
int h, int rw,
if (pte_update_flags(ctx, pte1, ret, rw) == 1) {
#if defined(TARGET_PPC64)
[Qemu-devel] [PATCH 09/27] Use hash more consistently in ppc mmu code
Currently, get_segment() has a variable called hash. However it doesn't
(quite) get the hash value for the ppc hashed page table. Instead it
gets the hash shifted - effectively the offset of the hash bucket within
the hash page table.
As well, as being different to the normal use of plain hash in the
architecture documentation, this usage necessitates some awkward 32/64
dependent masks and shifts which clutter up the path in get_segment().
This patch alters the code to use raw hash values through get_segment()
including storing raw hashes instead of pte group offsets in the ctx
structure. This cleans up the path noticeably.
This does necessitate 32/64 dependent shifts when the hash values are
taken out of the ctx structure and used, but those paths already have
32/64 bit variants so this is less awkward than it was in get_segment().
Signed-off-by: David Gibson d...@au1.ibm.com
---
target-ppc/cpu.h|5 ++-
target-ppc/helper.c | 95 --
2 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ead4566..cee1057 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -367,6 +367,9 @@ union ppc_tlb_t {
#define SDR_64_HTABSIZE0x001FULL
#endif /* defined(TARGET_PPC64 */
+#define HASH_PTE_SIZE_32 8
+#define HASH_PTE_SIZE_64 16
+
typedef struct ppc_slb_t ppc_slb_t;
struct ppc_slb_t {
uint64_t esid;
@@ -744,7 +747,7 @@ struct mmu_ctx_t {
target_phys_addr_t raddr; /* Real address */
target_phys_addr_t eaddr; /* Effective address */
int prot; /* Protection bits */
-target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
+target_phys_addr_t hash[2];/* Pagetable hash values */
target_ulong ptem; /* Virtual segment ID | API */
int key; /* Access key*/
int nx;/* Non-execute area */
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 68d2d9c..0efa2a8 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -567,21 +567,30 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx,
target_ulong virtual,
return ret;
}
+static inline target_phys_addr_t get_pteg_offset(CPUState *env,
+ target_phys_addr_t hash,
+ int pte_size)
+{
+return (hash * pte_size * 8) env-htab_mask;
+}
+
/* PTE table lookup */
-static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
-int type, int target_page_bits)
+static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h,
+int rw, int type, int target_page_bits)
{
-target_ulong base, pte0, pte1;
+target_phys_addr_t pteg_off;
+target_ulong pte0, pte1;
int i, good = -1;
int ret, r;
ret = -1; /* No entry found */
-base = ctx-pg_addr[h];
+pteg_off = get_pteg_offset(env, ctx-hash[h],
+ is_64b ? HASH_PTE_SIZE_64 : HASH_PTE_SIZE_32);
for (i = 0; i 8; i++) {
#if defined(TARGET_PPC64)
if (is_64b) {
-pte0 = ldq_phys(base + (i * 16));
-pte1 = ldq_phys(base + (i * 16) + 8);
+pte0 = ldq_phys(env-htab_base + pteg_off + (i * 16));
+pte1 = ldq_phys(env-htab_base + pteg_off + (i * 16) + 8);
/* We have a TLB that saves 4K pages, so let's
* split a huge page to 4k chunks */
@@ -592,17 +601,17 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b,
int h, int rw,
r = pte64_check(ctx, pte0, pte1, h, rw, type);
LOG_MMU(Load pte from TARGET_FMT_lx = TARGET_FMT_lx
TARGET_FMT_lx %d %d %d TARGET_FMT_lx \n,
-base + (i * 16), pte0, pte1, (int)(pte0 1), h,
+pteg_base + (i * 16), pte0, pte1, (int)(pte0 1), h,
(int)((pte0 1) 1), ctx-ptem);
} else
#endif
{
-pte0 = ldl_phys(base + (i * 8));
-pte1 = ldl_phys(base + (i * 8) + 4);
+pte0 = ldl_phys(env-htab_base + pteg_off + (i * 8));
+pte1 = ldl_phys(env-htab_base + pteg_off + (i * 8) + 4);
r = pte32_check(ctx, pte0, pte1, h, rw, type);
LOG_MMU(Load pte from TARGET_FMT_lx = TARGET_FMT_lx
TARGET_FMT_lx %d %d %d TARGET_FMT_lx \n,
-base + (i * 8), pte0, pte1, (int)(pte0 31), h,
+pteg_base + (i * 8), pte0, pte1, (int)(pte0 31), h,
(int)((pte0 6) 1), ctx-ptem);
}
switch (r) {
@@ -638,11 +647,13 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b,
int h, int rw,
if (pte_update_flags(ctx, pte1, ret, rw) == 1) {
#if defined(TARGET_PPC64)
[Qemu-devel] [PATCH 09/27] Use hash more consistently in ppc mmu code
Currently, get_segment() has a variable called hash. However it doesn't
(quite) get the hash value for the ppc hashed page table. Instead it
gets the hash shifted - effectively the offset of the hash bucket within
the hash page table.
As well, as being different to the normal use of plain hash in the
architecture documentation, this usage necessitates some awkward 32/64
dependent masks and shifts which clutter up the path in get_segment().
This patch alters the code to use raw hash values through get_segment()
including storing raw hashes instead of pte group offsets in the ctx
structure. This cleans up the path noticeably.
This does necessitate 32/64 dependent shifts when the hash values are
taken out of the ctx structure and used, but those paths already have
32/64 bit variants so this is less awkward than it was in get_segment().
Signed-off-by: David Gibson d...@au1.ibm.com
---
target-ppc/cpu.h|5 ++-
target-ppc/helper.c | 95 --
2 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ead4566..cee1057 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -367,6 +367,9 @@ union ppc_tlb_t {
#define SDR_64_HTABSIZE0x001FULL
#endif /* defined(TARGET_PPC64 */
+#define HASH_PTE_SIZE_32 8
+#define HASH_PTE_SIZE_64 16
+
typedef struct ppc_slb_t ppc_slb_t;
struct ppc_slb_t {
uint64_t esid;
@@ -744,7 +747,7 @@ struct mmu_ctx_t {
target_phys_addr_t raddr; /* Real address */
target_phys_addr_t eaddr; /* Effective address */
int prot; /* Protection bits */
-target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
+target_phys_addr_t hash[2];/* Pagetable hash values */
target_ulong ptem; /* Virtual segment ID | API */
int key; /* Access key*/
int nx;/* Non-execute area */
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 68d2d9c..0efa2a8 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -567,21 +567,30 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx,
target_ulong virtual,
return ret;
}
+static inline target_phys_addr_t get_pteg_offset(CPUState *env,
+ target_phys_addr_t hash,
+ int pte_size)
+{
+return (hash * pte_size * 8) env-htab_mask;
+}
+
/* PTE table lookup */
-static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
-int type, int target_page_bits)
+static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h,
+int rw, int type, int target_page_bits)
{
-target_ulong base, pte0, pte1;
+target_phys_addr_t pteg_off;
+target_ulong pte0, pte1;
int i, good = -1;
int ret, r;
ret = -1; /* No entry found */
-base = ctx-pg_addr[h];
+pteg_off = get_pteg_offset(env, ctx-hash[h],
+ is_64b ? HASH_PTE_SIZE_64 : HASH_PTE_SIZE_32);
for (i = 0; i 8; i++) {
#if defined(TARGET_PPC64)
if (is_64b) {
-pte0 = ldq_phys(base + (i * 16));
-pte1 = ldq_phys(base + (i * 16) + 8);
+pte0 = ldq_phys(env-htab_base + pteg_off + (i * 16));
+pte1 = ldq_phys(env-htab_base + pteg_off + (i * 16) + 8);
/* We have a TLB that saves 4K pages, so let's
* split a huge page to 4k chunks */
@@ -592,17 +601,17 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b,
int h, int rw,
r = pte64_check(ctx, pte0, pte1, h, rw, type);
LOG_MMU(Load pte from TARGET_FMT_lx = TARGET_FMT_lx
TARGET_FMT_lx %d %d %d TARGET_FMT_lx \n,
-base + (i * 16), pte0, pte1, (int)(pte0 1), h,
+pteg_base + (i * 16), pte0, pte1, (int)(pte0 1), h,
(int)((pte0 1) 1), ctx-ptem);
} else
#endif
{
-pte0 = ldl_phys(base + (i * 8));
-pte1 = ldl_phys(base + (i * 8) + 4);
+pte0 = ldl_phys(env-htab_base + pteg_off + (i * 8));
+pte1 = ldl_phys(env-htab_base + pteg_off + (i * 8) + 4);
r = pte32_check(ctx, pte0, pte1, h, rw, type);
LOG_MMU(Load pte from TARGET_FMT_lx = TARGET_FMT_lx
TARGET_FMT_lx %d %d %d TARGET_FMT_lx \n,
-base + (i * 8), pte0, pte1, (int)(pte0 31), h,
+pteg_base + (i * 8), pte0, pte1, (int)(pte0 31), h,
(int)((pte0 6) 1), ctx-ptem);
}
switch (r) {
@@ -638,11 +647,13 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b,
int h, int rw,
if (pte_update_flags(ctx, pte1, ret, rw) == 1) {
#if defined(TARGET_PPC64)
