[Qemu-devel] [PATCH 1/3] megasas: Add header file
This patch adds the header file for megasas. Signed-off-by: Hannes Reinecke h...@suse.de --- hw/mfi.h | 1248 ++ 1 files changed, 1248 insertions(+), 0 deletions(-) create mode 100644 hw/mfi.h diff --git a/hw/mfi.h b/hw/mfi.h new file mode 100644 index 000..8a82162 --- /dev/null +++ b/hw/mfi.h @@ -0,0 +1,1248 @@ +/* + * NetBSD header file, copied from + * http://gitorious.org/freebsd/freebsd/blobs/HEAD/sys/dev/mfi/mfireg.h + */ +/*- + * Copyright (c) 2006 IronPort Systems + * Copyright (c) 2007 LSI Corp. + * Copyright (c) 2007 Rajesh Prabhakaran. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef MFI_REG_H +#define MFI_REG_H + +/* + * MegaRAID SAS MFI firmware definitions + */ + +/* + * Start with the register set. All registers are 32 bits wide. + * The usual Intel IOP style setup. + */ +#define MFI_IMSG0 0x10/* Inbound message 0 */ +#define MFI_IMSG1 0x14/* Inbound message 1 */ +#define MFI_OMSG0 0x18/* Outbound message 0 */ +#define MFI_OMSG1 0x1c/* Outbound message 1 */ +#define MFI_IDB 0x20/* Inbound doorbell */ +#define MFI_ISTS 0x24/* Inbound interrupt status */ +#define MFI_IMSK 0x28/* Inbound interrupt mask */ +#define MFI_ODB 0x2c/* Outbound doorbell */ +#define MFI_OSTS 0x30/* Outbound interrupt status */ +#define MFI_OMSK 0x34/* Outbound interrupt mask */ +#define MFI_IQP 0x40/* Inbound queue port */ +#define MFI_OQP 0x44/* Outbound queue port */ + +/* + * 1078 specific related register + */ +#define MFI_ODR00x9c/* outbound doorbell register0 */ +#define MFI_ODCR0 0xa0/* outbound doorbell clear register0 */ +#define MFI_OSP00xb0/* outbound scratch pad0 */ +#define MFI_IQPL0xc0/* Inbound queue port (low bytes) */ +#define MFI_IQPH0xc4/* Inbound queue port (high bytes) */ +#define MFI_DIAG0xf8/* Host diag */ +#define MFI_SEQ 0xfc/* Sequencer offset */ +#define MFI_1078_EIM0x8004 /* 1078 enable intrrupt mask */ +#define MFI_RMI 0x2 /* reply message interrupt */ +#define MFI_1078_RM 0x8000 /* reply 1078 message interrupt */ +#define MFI_ODC 0x4 /* outbound doorbell change interrupt */ + +/* + * gen2 specific changes + */ +#define MFI_GEN2_EIM0x0005 /* gen2 enable interrupt mask */ +#define MFI_GEN2_RM 0x0001 /* reply gen2 message interrupt */ + +/* + * skinny specific changes + */ +#define MFI_SKINNY_IDB 0x00/* Inbound doorbell is at 0x00 for skinny */ +#define MFI_SKINNY_RM 0x0001 /* reply skinny message interrupt */ + +/* Bits for MFI_OSTS */ +#define MFI_OSTS_INTR_VALID 0x0002 + +/* + * Firmware state values. Found in OMSG0 during initialization. + */ +#define MFI_FWSTATE_MASK0xf000 +#define MFI_FWSTATE_UNDEFINED 0x +#define MFI_FWSTATE_BB_INIT 0x1000 +#define MFI_FWSTATE_FW_INIT 0x4000 +#define MFI_FWSTATE_WAIT_HANDSHAKE 0x6000 +#define MFI_FWSTATE_FW_INIT_2 0x7000 +#define MFI_FWSTATE_DEVICE_SCAN 0x8000 +#define MFI_FWSTATE_BOOT_MSG_PENDING0x9000 +#define MFI_FWSTATE_FLUSH_CACHE 0xa000 +#define MFI_FWSTATE_READY 0xb000 +#define MFI_FWSTATE_OPERATIONAL 0xc000 +#define MFI_FWSTATE_FAULT 0xf000 +#define MFI_FWSTATE_MAXSGL_MASK 0x00ff +#define MFI_FWSTATE_MAXCMD_MASK 0x +#define MFI_FWSTATE_MSIX_SUPPORTED 0x0400 +#define
[Qemu-devel] [PATCH 1/3] megasas: Add header file
This patch adds the header file for megasas. Signed-off-by: Hannes Reinecke h...@suse.de --- hw/mfi.h | 1248 ++ 1 files changed, 1248 insertions(+), 0 deletions(-) create mode 100644 hw/mfi.h diff --git a/hw/mfi.h b/hw/mfi.h new file mode 100644 index 000..8a82162 --- /dev/null +++ b/hw/mfi.h @@ -0,0 +1,1248 @@ +/* + * NetBSD header file, copied from + * http://gitorious.org/freebsd/freebsd/blobs/HEAD/sys/dev/mfi/mfireg.h + */ +/*- + * Copyright (c) 2006 IronPort Systems + * Copyright (c) 2007 LSI Corp. + * Copyright (c) 2007 Rajesh Prabhakaran. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef MFI_REG_H +#define MFI_REG_H + +/* + * MegaRAID SAS MFI firmware definitions + */ + +/* + * Start with the register set. All registers are 32 bits wide. + * The usual Intel IOP style setup. + */ +#define MFI_IMSG0 0x10/* Inbound message 0 */ +#define MFI_IMSG1 0x14/* Inbound message 1 */ +#define MFI_OMSG0 0x18/* Outbound message 0 */ +#define MFI_OMSG1 0x1c/* Outbound message 1 */ +#define MFI_IDB 0x20/* Inbound doorbell */ +#define MFI_ISTS 0x24/* Inbound interrupt status */ +#define MFI_IMSK 0x28/* Inbound interrupt mask */ +#define MFI_ODB 0x2c/* Outbound doorbell */ +#define MFI_OSTS 0x30/* Outbound interrupt status */ +#define MFI_OMSK 0x34/* Outbound interrupt mask */ +#define MFI_IQP 0x40/* Inbound queue port */ +#define MFI_OQP 0x44/* Outbound queue port */ + +/* + * 1078 specific related register + */ +#define MFI_ODR00x9c/* outbound doorbell register0 */ +#define MFI_ODCR0 0xa0/* outbound doorbell clear register0 */ +#define MFI_OSP00xb0/* outbound scratch pad0 */ +#define MFI_IQPL0xc0/* Inbound queue port (low bytes) */ +#define MFI_IQPH0xc4/* Inbound queue port (high bytes) */ +#define MFI_DIAG0xf8/* Host diag */ +#define MFI_SEQ 0xfc/* Sequencer offset */ +#define MFI_1078_EIM0x8004 /* 1078 enable intrrupt mask */ +#define MFI_RMI 0x2 /* reply message interrupt */ +#define MFI_1078_RM 0x8000 /* reply 1078 message interrupt */ +#define MFI_ODC 0x4 /* outbound doorbell change interrupt */ + +/* + * gen2 specific changes + */ +#define MFI_GEN2_EIM0x0005 /* gen2 enable interrupt mask */ +#define MFI_GEN2_RM 0x0001 /* reply gen2 message interrupt */ + +/* + * skinny specific changes + */ +#define MFI_SKINNY_IDB 0x00/* Inbound doorbell is at 0x00 for skinny */ +#define MFI_SKINNY_RM 0x0001 /* reply skinny message interrupt */ + +/* Bits for MFI_OSTS */ +#define MFI_OSTS_INTR_VALID 0x0002 + +/* + * Firmware state values. Found in OMSG0 during initialization. + */ +#define MFI_FWSTATE_MASK0xf000 +#define MFI_FWSTATE_UNDEFINED 0x +#define MFI_FWSTATE_BB_INIT 0x1000 +#define MFI_FWSTATE_FW_INIT 0x4000 +#define MFI_FWSTATE_WAIT_HANDSHAKE 0x6000 +#define MFI_FWSTATE_FW_INIT_2 0x7000 +#define MFI_FWSTATE_DEVICE_SCAN 0x8000 +#define MFI_FWSTATE_BOOT_MSG_PENDING0x9000 +#define MFI_FWSTATE_FLUSH_CACHE 0xa000 +#define MFI_FWSTATE_READY 0xb000 +#define MFI_FWSTATE_OPERATIONAL 0xc000 +#define MFI_FWSTATE_FAULT 0xf000 +#define MFI_FWSTATE_MAXSGL_MASK 0x00ff +#define MFI_FWSTATE_MAXCMD_MASK 0x +#define MFI_FWSTATE_MSIX_SUPPORTED 0x0400 +#define
[Qemu-devel] [PATCH 1/3] megasas: Add header file
This patch adds the header file for megasas. Signed-off-by: Hannes Reinecke h...@suse.de --- hw/mfi.h | 1248 ++ 1 files changed, 1248 insertions(+), 0 deletions(-) create mode 100644 hw/mfi.h diff --git a/hw/mfi.h b/hw/mfi.h new file mode 100644 index 000..8a82162 --- /dev/null +++ b/hw/mfi.h @@ -0,0 +1,1248 @@ +/* + * NetBSD header file, copied from + * http://gitorious.org/freebsd/freebsd/blobs/HEAD/sys/dev/mfi/mfireg.h + */ +/*- + * Copyright (c) 2006 IronPort Systems + * Copyright (c) 2007 LSI Corp. + * Copyright (c) 2007 Rajesh Prabhakaran. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef MFI_REG_H +#define MFI_REG_H + +/* + * MegaRAID SAS MFI firmware definitions + */ + +/* + * Start with the register set. All registers are 32 bits wide. + * The usual Intel IOP style setup. + */ +#define MFI_IMSG0 0x10/* Inbound message 0 */ +#define MFI_IMSG1 0x14/* Inbound message 1 */ +#define MFI_OMSG0 0x18/* Outbound message 0 */ +#define MFI_OMSG1 0x1c/* Outbound message 1 */ +#define MFI_IDB 0x20/* Inbound doorbell */ +#define MFI_ISTS 0x24/* Inbound interrupt status */ +#define MFI_IMSK 0x28/* Inbound interrupt mask */ +#define MFI_ODB 0x2c/* Outbound doorbell */ +#define MFI_OSTS 0x30/* Outbound interrupt status */ +#define MFI_OMSK 0x34/* Outbound interrupt mask */ +#define MFI_IQP 0x40/* Inbound queue port */ +#define MFI_OQP 0x44/* Outbound queue port */ + +/* + * 1078 specific related register + */ +#define MFI_ODR00x9c/* outbound doorbell register0 */ +#define MFI_ODCR0 0xa0/* outbound doorbell clear register0 */ +#define MFI_OSP00xb0/* outbound scratch pad0 */ +#define MFI_IQPL0xc0/* Inbound queue port (low bytes) */ +#define MFI_IQPH0xc4/* Inbound queue port (high bytes) */ +#define MFI_DIAG0xf8/* Host diag */ +#define MFI_SEQ 0xfc/* Sequencer offset */ +#define MFI_1078_EIM0x8004 /* 1078 enable intrrupt mask */ +#define MFI_RMI 0x2 /* reply message interrupt */ +#define MFI_1078_RM 0x8000 /* reply 1078 message interrupt */ +#define MFI_ODC 0x4 /* outbound doorbell change interrupt */ + +/* + * gen2 specific changes + */ +#define MFI_GEN2_EIM0x0005 /* gen2 enable interrupt mask */ +#define MFI_GEN2_RM 0x0001 /* reply gen2 message interrupt */ + +/* + * skinny specific changes + */ +#define MFI_SKINNY_IDB 0x00/* Inbound doorbell is at 0x00 for skinny */ +#define MFI_SKINNY_RM 0x0001 /* reply skinny message interrupt */ + +/* Bits for MFI_OSTS */ +#define MFI_OSTS_INTR_VALID 0x0002 + +/* + * Firmware state values. Found in OMSG0 during initialization. + */ +#define MFI_FWSTATE_MASK0xf000 +#define MFI_FWSTATE_UNDEFINED 0x +#define MFI_FWSTATE_BB_INIT 0x1000 +#define MFI_FWSTATE_FW_INIT 0x4000 +#define MFI_FWSTATE_WAIT_HANDSHAKE 0x6000 +#define MFI_FWSTATE_FW_INIT_2 0x7000 +#define MFI_FWSTATE_DEVICE_SCAN 0x8000 +#define MFI_FWSTATE_BOOT_MSG_PENDING0x9000 +#define MFI_FWSTATE_FLUSH_CACHE 0xa000 +#define MFI_FWSTATE_READY 0xb000 +#define MFI_FWSTATE_OPERATIONAL 0xc000 +#define MFI_FWSTATE_FAULT 0xf000 +#define MFI_FWSTATE_MAXSGL_MASK 0x00ff +#define MFI_FWSTATE_MAXCMD_MASK 0x +#define MFI_FWSTATE_MSIX_SUPPORTED 0x0400 +#define
