Re: [Qemu-devel] [PATCH 11/17] target/arm: Implement the STGP instruction

[Peter Maydell]

On Mon, 14 Jan 2019 at 01:12, Richard Henderson
 wrote:
>
> Signed-off-by: Richard Henderson 
> ---
>  target/arm/translate-a64.c | 18 --
>  1 file changed, 16 insertions(+), 2 deletions(-)

Same remark as for patch 10.

thanks
-- PMM

[Qemu-devel] [PATCH 11/17] target/arm: Implement the STGP instruction

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 target/arm/translate-a64.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 60865945e4..911d6f06b3 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2696,7 +2696,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
  * +-+---+---+---+---+---+---+---+--+--+
  *
  * opc: LDP/STP/LDNP/STNP00 -> 32 bit, 10 -> 64 bit
- *  LDPSW01
+ *  LDPSW/STGP   01
  *  LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
  *   V: 0 -> GPR, 1 -> Vector
  * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
@@ -2721,6 +2721,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t 
insn)
 bool is_signed = false;
 bool postindex = false;
 bool wback = false;
+bool set_tag = false;
 
 TCGv_i64 clean_addr, dirty_addr;
 
@@ -2733,6 +2734,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t 
insn)
 
 if (is_vector) {
 size = 2 + opc;
+} else if (opc == 1 && !is_load) {
+/* STGP */
+if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) {
+unallocated_encoding(s);
+return;
+}
+size = 3;
+set_tag = true;
 } else {
 size = 2 + extract32(opc, 1, 1);
 is_signed = extract32(opc, 0, 1);
@@ -2783,7 +2792,12 @@ static void disas_ldst_pair(DisasContext *s, uint32_t 
insn)
 if (!postindex) {
 tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
 }
-clean_addr = clean_data_tbi(s, dirty_addr, rn == 31);
+if (set_tag) {
+clean_addr = new_tmp_a64(s);
+gen_helper_stg(clean_addr, cpu_env, dirty_addr);
+} else {
+clean_addr = clean_data_tbi(s, dirty_addr, rn == 31);
+}
 
 if (is_vector) {
 if (is_load) {
-- 
2.17.2