Re: [Qemu-devel] [PATCH 2/3] target/ppc: convert to DisasContextBase

[Richard Henderson]

On 02/14/2018 07:14 PM, Emilio G. Cota wrote:
> A couple of notes:
> 
> - removed ctx->nip in favour of base->pc_next. Yes, it is annoying,
>   but didn't want to waste its 4 bytes.
> 
> - ctx->singlestep_enabled does a lot more than
>   base.singlestep_enabled; this confused me at first.
> 
> Signed-off-by: Emilio G. Cota 
> ---
>  target/ppc/translate.c  | 129 
> +++-
>  target/ppc/translate/dfp-impl.inc.c |  16 ++---
>  target/ppc/translate_init.c |  32 -
>  3 files changed, 91 insertions(+), 86 deletions(-)

Reviewed-by: Richard Henderson 


r~

[Qemu-devel] [PATCH 2/3] target/ppc: convert to DisasContextBase

[Emilio G. Cota]

A couple of notes:

- removed ctx->nip in favour of base->pc_next. Yes, it is annoying,
  but didn't want to waste its 4 bytes.

- ctx->singlestep_enabled does a lot more than
  base.singlestep_enabled; this confused me at first.

Signed-off-by: Emilio G. Cota 
---
 target/ppc/translate.c  | 129 +++-
 target/ppc/translate/dfp-impl.inc.c |  16 ++---
 target/ppc/translate_init.c |  32 -
 3 files changed, 91 insertions(+), 86 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4132f67..6e35daa 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -31,6 +31,7 @@
 #include "exec/helper-gen.h"
 
 #include "trace-tcg.h"
+#include "exec/translator.h"
 #include "exec/log.h"
 
 
@@ -187,8 +188,7 @@ void ppc_translate_init(void)
 
 /* internal defines */
 struct DisasContext {
-struct TranslationBlock *tb;
-target_ulong nip;
+DisasContextBase base;
 uint32_t opcode;
 uint32_t exception;
 /* Routine used to access memory */
@@ -275,7 +275,7 @@ static void gen_exception_err(DisasContext *ctx, uint32_t 
excp, uint32_t error)
  * the faulting instruction
  */
 if (ctx->exception == POWERPC_EXCP_NONE) {
-gen_update_nip(ctx, ctx->nip - 4);
+gen_update_nip(ctx, ctx->base.pc_next - 4);
 }
 t0 = tcg_const_i32(excp);
 t1 = tcg_const_i32(error);
@@ -293,7 +293,7 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
  * the faulting instruction
  */
 if (ctx->exception == POWERPC_EXCP_NONE) {
-gen_update_nip(ctx, ctx->nip - 4);
+gen_update_nip(ctx, ctx->base.pc_next - 4);
 }
 t0 = tcg_const_i32(excp);
 gen_helper_raise_exception(cpu_env, t0);
@@ -322,7 +322,7 @@ static void gen_debug_exception(DisasContext *ctx)
  */
 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
 (ctx->exception != POWERPC_EXCP_SYNC)) {
-gen_update_nip(ctx, ctx->nip);
+gen_update_nip(ctx, ctx->base.pc_next);
 }
 t0 = tcg_const_i32(EXCP_DEBUG);
 gen_helper_raise_exception(cpu_env, t0);
@@ -349,7 +349,7 @@ static inline void gen_hvpriv_exception(DisasContext *ctx, 
uint32_t error)
 /* Stop translation */
 static inline void gen_stop_exception(DisasContext *ctx)
 {
-gen_update_nip(ctx, ctx->nip);
+gen_update_nip(ctx, ctx->base.pc_next);
 ctx->exception = POWERPC_EXCP_STOP;
 }
 
@@ -978,7 +978,7 @@ static void gen_addpcis(DisasContext *ctx)
 {
 target_long d = DX(ctx->opcode);
 
-tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
+tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
 }
 
 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
@@ -1580,7 +1580,7 @@ static void gen_pause(DisasContext *ctx)
 tcg_temp_free_i32(t0);
 
 /* Stop translation, this gives other CPUs a chance to run */
-gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
+gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
 }
 #endif /* defined(TARGET_PPC64) */
 
@@ -2397,7 +2397,7 @@ static inline void gen_check_align(DisasContext *ctx, 
TCGv EA, int mask)
 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
 t2 = tcg_const_i32(ctx->opcode & 0x03FF);
-gen_update_nip(ctx, ctx->nip - 4);
+gen_update_nip(ctx, ctx->base.pc_next - 4);
 gen_helper_raise_exception_err(cpu_env, t1, t2);
 tcg_temp_free_i32(t1);
 tcg_temp_free_i32(t2);
@@ -3322,7 +3322,7 @@ static void gen_wait(DisasContext *ctx)
-offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
 tcg_temp_free_i32(t0);
 /* Stop translation, as the CPU is supposed to sleep from now */
-gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
+gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
 }
 
 #if defined(TARGET_PPC64)
@@ -3407,7 +3407,7 @@ static inline bool use_goto_tb(DisasContext *ctx, 
target_ulong dest)
 }
 
 #ifndef CONFIG_USER_ONLY
-return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
+return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
 #else
 return true;
 #endif
@@ -3422,7 +3422,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, 
target_ulong dest)
 if (use_goto_tb(ctx, dest)) {
 tcg_gen_goto_tb(n);
 tcg_gen_movi_tl(cpu_nip, dest & ~3);
-tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
+tcg_gen_exit_tb((uintptr_t)ctx->base.tb + n);
 } else {
 tcg_gen_movi_tl(cpu_nip, dest & ~3);
 if (unlikely(ctx->singlestep_enabled)) {
@@ -3458,14 +3458,14 @@ static void gen_b(DisasContext *ctx)
 li = LI(ctx->opcode);
 li = (li ^ 0x0200) - 0x0200;
 if (likely(AA(ctx->opcode) == 0)) {
-target = ctx->nip + li - 4;
+target = ctx->base.pc_next + li - 4;
 } else {
 target = li;
 }
 if (LK(ctx->opcode)) {
-gen_setlr(ctx, ctx->nip);
+gen_