Convert the VFP VMOV (immediate) instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 129 +
target/arm/translate.c | 27 +--
target/arm/vfp.decode | 5 ++
3 files changed, 136 insertions(+), 25 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index ba6506a378c..a2eeb6cb511 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1602,3 +1602,132 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_sp *a)
return true;
}
+
+static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
+{
+uint32_t delta_d = 0;
+uint32_t bank_mask = 0;
+int veclen = s->vec_len;
+TCGv_i32 fd;
+uint32_t n, i, vd;
+
+vd = a->vd;
+
+if (!dc_isar_feature(aa32_fpshvec, s) &&
+(veclen != 0 || s->vec_stride != 0)) {
+return false;
+}
+
+if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+return false;
+}
+
+if (!vfp_access_check(s)) {
+return true;
+}
+
+if (veclen > 0) {
+bank_mask = 0x18;
+/* Figure out what type of vector operation this is. */
+if ((vd & bank_mask) == 0) {
+/* scalar */
+veclen = 0;
+} else {
+delta_d = s->vec_stride + 1;
+}
+}
+
+n = (a->imm4h << 28) & 0x8000;
+i = ((a->imm4h << 4) & 0x70) | a->imm4l;
+if (i & 0x40) {
+i |= 0x780;
+} else {
+i |= 0x800;
+}
+n |= i << 19;
+
+fd = tcg_temp_new_i32();
+tcg_gen_movi_i32(fd, n);
+
+for (;;) {
+neon_store_reg32(fd, vd);
+
+if (veclen == 0) {
+break;
+}
+
+/* Set up the operands for the next iteration */
+veclen--;
+vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask);
+}
+
+tcg_temp_free_i32(fd);
+return true;
+}
+
+static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
+{
+uint32_t delta_d = 0;
+uint32_t bank_mask = 0;
+int veclen = s->vec_len;
+TCGv_i64 fd;
+uint32_t n, i, vd;
+
+vd = a->vd;
+
+/* UNDEF accesses to D16-D31 if they don't exist. */
+if (!dc_isar_feature(aa32_fp_d32, s) && (vd & 0x10)) {
+return false;
+}
+
+if (!dc_isar_feature(aa32_fpshvec, s) &&
+(veclen != 0 || s->vec_stride != 0)) {
+return false;
+}
+
+if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+return false;
+}
+
+if (!vfp_access_check(s)) {
+return true;
+}
+
+if (veclen > 0) {
+bank_mask = 0xc;
+/* Figure out what type of vector operation this is. */
+if ((vd & bank_mask) == 0) {
+/* scalar */
+veclen = 0;
+} else {
+delta_d = (s->vec_stride >> 1) + 1;
+}
+}
+
+n = (a->imm4h << 28) & 0x8000;
+i = ((a->imm4h << 4) & 0x70) | a->imm4l;
+if (i & 0x40) {
+i |= 0x3f80;
+} else {
+i |= 0x4000;
+}
+n |= i << 16;
+
+fd = tcg_temp_new_i64();
+tcg_gen_movi_i64(fd, ((uint64_t)n) << 32);
+
+for (;;) {
+neon_store_reg64(fd, vd);
+
+if (veclen == 0) {
+break;
+}
+
+/* Set up the operands for the next iteration */
+veclen--;
+vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask);
+}
+
+tcg_temp_free_i64(fd);
+return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e8785fd26e6..38ec026d865 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3033,7 +3033,7 @@ static void gen_neon_dup_high16(TCGv_i32 var)
*/
static int disas_vfp_insn(DisasContext *s, uint32_t insn)
{
-uint32_t rd, rn, rm, op, i, n, delta_d, delta_m, bank_mask;
+uint32_t rd, rn, rm, op, delta_d, delta_m, bank_mask;
int dp, veclen;
TCGv_i32 tmp;
TCGv_i32 tmp2;
@@ -3093,7 +3093,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
rn = VFP_SREG_N(insn);
switch (op) {
-case 0 ... 13:
+case 0 ... 14:
/* Already handled by decodetree */
return 1;
default:
@@ -3279,29 +3279,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
for (;;) {
/* Perform the calculation. */
switch (op) {
-case 14: /* fconst */
-if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
-return 1;
-}
-
-n = (insn << 12) & 0x8000;
-i = ((insn >> 12) & 0x70) | (insn & 0xf);
-if (dp) {
-if (i & 0x40)
-i |= 0x3f80;
-else
-i |= 0x4000;
-n |= i << 16;
-tcg_gen_movi_i64(cpu_F0d,
