[Qemu-devel] [PATCH 4/7] PPC: Add another 64 bits to instruction feature mask
To enable quick runtime detection of instruction groups to the currently
selected CPU emulation, we have a feature mask of what exactly the respective
instruction supports.
This feature mask is 64 bits long and we just successfully exceeded those 64
bits. To add more features, we need to think of something.
The easiest solution that came to my mind was to simply add another 64 bits
that we can also match on. Since the comparison is only done on start of the
qemu process to generate an internal opcode calling table, we should be fine
on any performance penalties here.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/cpu.h|1 +
target-ppc/translate.c | 25 +++--
target-ppc/translate_init.c | 123 +++
3 files changed, 110 insertions(+), 39 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index c6b2255..2a7431c 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -722,6 +722,7 @@ struct CPUPPCState {
int bfd_mach;
uint32_t flags;
uint64_t insns_flags;
+uint64_t insns_flags2;
#if defined(TARGET_PPC64) !defined(CONFIG_USER_ONLY)
target_phys_addr_t vpa;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 99f572a..95813f2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -201,6 +201,8 @@ struct opc_handler_t {
uint32_t inval;
/* instruction type */
uint64_t type;
+/* extended instruction type */
+uint64_t type2;
/* handler */
void (*handler)(DisasContext *ctx);
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
@@ -314,10 +316,16 @@ static inline void gen_sync_exception(DisasContext *ctx)
}
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
-GEN_OPCODE(name, opc1, opc2, opc3, inval, type)
+GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
+
+#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
+GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
-GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type)
+GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
+
+#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
+GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
typedef struct opcode_t {
unsigned char opc1, opc2, opc3;
@@ -457,7 +465,7 @@ static inline target_ulong MASK(uint32_t start, uint32_t
end)
/* PowerPC instructions table*/
#if defined(DO_PPC_STATISTICS)
-#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
+#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)\
{ \
.opc1 = op1, \
.opc2 = op2, \
@@ -466,12 +474,13 @@ static inline target_ulong MASK(uint32_t start, uint32_t
end)
.handler = { \
.inval = invl, \
.type = _typ, \
+.type2 = _typ2, \
.handler = gen_##name, \
.oname = stringify(name), \
},\
.oname = stringify(name), \
}
-#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)\
+#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
{ \
.opc1 = op1, \
.opc2 = op2, \
@@ -480,13 +489,14 @@ static inline target_ulong MASK(uint32_t start, uint32_t
end)
.handler = { \
.inval = invl, \
.type = _typ, \
+.type2 = _typ2, \
.handler = gen_##name, \
.oname = onam,\
},\
.oname = onam,\
}
#else
-#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)
[Qemu-devel] [PATCH 4/7] PPC: Add another 64 bits to instruction feature mask
To enable quick runtime detection of instruction groups to the currently
selected CPU emulation, we have a feature mask of what exactly the respective
instruction supports.
This feature mask is 64 bits long and we just successfully exceeded those 64
bits. To add more features, we need to think of something.
The easiest solution that came to my mind was to simply add another 64 bits
that we can also match on. Since the comparison is only done on start of the
qemu process to generate an internal opcode calling table, we should be fine
on any performance penalties here.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/cpu.h|1 +
target-ppc/translate.c | 25 +++--
target-ppc/translate_init.c | 123 +++
3 files changed, 110 insertions(+), 39 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index c6b2255..2a7431c 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -722,6 +722,7 @@ struct CPUPPCState {
int bfd_mach;
uint32_t flags;
uint64_t insns_flags;
+uint64_t insns_flags2;
#if defined(TARGET_PPC64) !defined(CONFIG_USER_ONLY)
target_phys_addr_t vpa;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 99f572a..95813f2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -201,6 +201,8 @@ struct opc_handler_t {
uint32_t inval;
/* instruction type */
uint64_t type;
+/* extended instruction type */
+uint64_t type2;
/* handler */
void (*handler)(DisasContext *ctx);
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
@@ -314,10 +316,16 @@ static inline void gen_sync_exception(DisasContext *ctx)
}
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
-GEN_OPCODE(name, opc1, opc2, opc3, inval, type)
+GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
+
+#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
+GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
-GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type)
+GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
+
+#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
+GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
typedef struct opcode_t {
unsigned char opc1, opc2, opc3;
@@ -457,7 +465,7 @@ static inline target_ulong MASK(uint32_t start, uint32_t
end)
/* PowerPC instructions table*/
#if defined(DO_PPC_STATISTICS)
-#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
+#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)\
{ \
.opc1 = op1, \
.opc2 = op2, \
@@ -466,12 +474,13 @@ static inline target_ulong MASK(uint32_t start, uint32_t
end)
.handler = { \
.inval = invl, \
.type = _typ, \
+.type2 = _typ2, \
.handler = gen_##name, \
.oname = stringify(name), \
},\
.oname = stringify(name), \
}
-#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)\
+#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
{ \
.opc1 = op1, \
.opc2 = op2, \
@@ -480,13 +489,14 @@ static inline target_ulong MASK(uint32_t start, uint32_t
end)
.handler = { \
.inval = invl, \
.type = _typ, \
+.type2 = _typ2, \
.handler = gen_##name, \
.oname = onam,\
},\
.oname = onam,\
}
#else
-#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)
[Qemu-devel] [PATCH 4/7] PPC: Add another 64 bits to instruction feature mask
To enable quick runtime detection of instruction groups to the currently
selected CPU emulation, we have a feature mask of what exactly the respective
instruction supports.
This feature mask is 64 bits long and we just successfully exceeded those 64
bits. To add more features, we need to think of something.
The easiest solution that came to my mind was to simply add another 64 bits
that we can also match on. Since the comparison is only done on start of the
qemu process to generate an internal opcode calling table, we should be fine
on any performance penalties here.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/cpu.h|1 +
target-ppc/translate.c | 25 +++--
target-ppc/translate_init.c | 123 +++
3 files changed, 110 insertions(+), 39 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index c6b2255..2a7431c 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -722,6 +722,7 @@ struct CPUPPCState {
int bfd_mach;
uint32_t flags;
uint64_t insns_flags;
+uint64_t insns_flags2;
#if defined(TARGET_PPC64) !defined(CONFIG_USER_ONLY)
target_phys_addr_t vpa;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 99f572a..95813f2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -201,6 +201,8 @@ struct opc_handler_t {
uint32_t inval;
/* instruction type */
uint64_t type;
+/* extended instruction type */
+uint64_t type2;
/* handler */
void (*handler)(DisasContext *ctx);
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
@@ -314,10 +316,16 @@ static inline void gen_sync_exception(DisasContext *ctx)
}
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
-GEN_OPCODE(name, opc1, opc2, opc3, inval, type)
+GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
+
+#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
+GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
-GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type)
+GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
+
+#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
+GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
typedef struct opcode_t {
unsigned char opc1, opc2, opc3;
@@ -457,7 +465,7 @@ static inline target_ulong MASK(uint32_t start, uint32_t
end)
/* PowerPC instructions table*/
#if defined(DO_PPC_STATISTICS)
-#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
+#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)\
{ \
.opc1 = op1, \
.opc2 = op2, \
@@ -466,12 +474,13 @@ static inline target_ulong MASK(uint32_t start, uint32_t
end)
.handler = { \
.inval = invl, \
.type = _typ, \
+.type2 = _typ2, \
.handler = gen_##name, \
.oname = stringify(name), \
},\
.oname = stringify(name), \
}
-#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)\
+#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
{ \
.opc1 = op1, \
.opc2 = op2, \
@@ -480,13 +489,14 @@ static inline target_ulong MASK(uint32_t start, uint32_t
end)
.handler = { \
.inval = invl, \
.type = _typ, \
+.type2 = _typ2, \
.handler = gen_##name, \
.oname = onam,\
},\
.oname = onam,\
}
#else
-#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)
