Re: [Qemu-devel] [PATCH 4/7] target/arm/translate-a64: Don't underdecode SIMD ld/st single

[Laurent Desnogues]

On Fri, Jan 25, 2019 at 7:26 PM Peter Maydell  wrote:
>
> In the AdvSIMD load/store single structure encodings, the
> non-post-indexed case should have zeroes in [20:16] (which is the
> Rm field for the post-indexed case). Bit 31 must also be zero
> (a check we got right in ldst_multiple but not here). Correctly
> UNDEF these unallocated encodings.
>
> Reported-by: Laurent Desnogues 
> Signed-off-by: Peter Maydell 

Reviewed-by: Laurent Desnogues 

Thanks,

Laurent

> ---
>  target/arm/translate-a64.c | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index c1f0cad7691..2cade64ed25 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -3409,6 +3409,7 @@ static void disas_ldst_single_struct(DisasContext *s, 
> uint32_t insn)
>  {
>  int rt = extract32(insn, 0, 5);
>  int rn = extract32(insn, 5, 5);
> +int rm = extract32(insn, 16, 5);
>  int size = extract32(insn, 10, 2);
>  int S = extract32(insn, 12, 1);
>  int opc = extract32(insn, 13, 3);
> @@ -3424,6 +3425,15 @@ static void disas_ldst_single_struct(DisasContext *s, 
> uint32_t insn)
>  int ebytes, xs;
>  TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
>
> +if (extract32(insn, 31, 1)) {
> +unallocated_encoding(s);
> +return;
> +}
> +if (!is_postidx && rm != 0) {
> +unallocated_encoding(s);
> +return;
> +}
> +
>  switch (scale) {
>  case 3:
>  if (!is_load || S) {
> @@ -3501,7 +3511,6 @@ static void disas_ldst_single_struct(DisasContext *s, 
> uint32_t insn)
>  }
>
>  if (is_postidx) {
> -int rm = extract32(insn, 16, 5);
>  if (rm == 31) {
>  tcg_gen_mov_i64(tcg_rn, tcg_addr);
>  } else {
> --
> 2.20.1
>

[Qemu-devel] [PATCH 4/7] target/arm/translate-a64: Don't underdecode SIMD ld/st single

[Peter Maydell]

In the AdvSIMD load/store single structure encodings, the
non-post-indexed case should have zeroes in [20:16] (which is the
Rm field for the post-indexed case). Bit 31 must also be zero
(a check we got right in ldst_multiple but not here). Correctly
UNDEF these unallocated encodings.

Reported-by: Laurent Desnogues 
Signed-off-by: Peter Maydell 
---
 target/arm/translate-a64.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c1f0cad7691..2cade64ed25 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3409,6 +3409,7 @@ static void disas_ldst_single_struct(DisasContext *s, 
uint32_t insn)
 {
 int rt = extract32(insn, 0, 5);
 int rn = extract32(insn, 5, 5);
+int rm = extract32(insn, 16, 5);
 int size = extract32(insn, 10, 2);
 int S = extract32(insn, 12, 1);
 int opc = extract32(insn, 13, 3);
@@ -3424,6 +3425,15 @@ static void disas_ldst_single_struct(DisasContext *s, 
uint32_t insn)
 int ebytes, xs;
 TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
 
+if (extract32(insn, 31, 1)) {
+unallocated_encoding(s);
+return;
+}
+if (!is_postidx && rm != 0) {
+unallocated_encoding(s);
+return;
+}
+
 switch (scale) {
 case 3:
 if (!is_load || S) {
@@ -3501,7 +3511,6 @@ static void disas_ldst_single_struct(DisasContext *s, 
uint32_t insn)
 }
 
 if (is_postidx) {
-int rm = extract32(insn, 16, 5);
 if (rm == 31) {
 tcg_gen_mov_i64(tcg_rn, tcg_addr);
 } else {
-- 
2.20.1