[Qemu-devel] [PATCH 45/50] mips: move CP0 functions out of cpu.h
These are here for historical reasons: they are needed from both gdbstub.c and op_helper.c, and the latter was compiled with fixed AREG0. It is not needed anymore, so uninline them. Signed-off-by: Paolo Bonzini--- target-mips/cpu.h| 113 ++- target-mips/helper.c | 108 2 files changed, 112 insertions(+), 109 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 0636327..951267a 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -1035,115 +1035,10 @@ static inline void compute_hflags(CPUMIPSState *env) } } -#ifndef CONFIG_USER_ONLY -static inline void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global) -{ -MIPSCPU *cpu = mips_env_get_cpu(env); - -/* Flush qemu's TLB and discard all shadowed entries. */ -tlb_flush(CPU(cpu), flush_global); -env->tlb->tlb_in_use = env->tlb->nb_tlb; -} - -/* Called for updates to CP0_Status. */ -static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ -int32_t tcstatus, *tcst; -uint32_t v = cpu->CP0_Status; -uint32_t cu, mx, asid, ksu; -uint32_t mask = ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - -cu = (v >> CP0St_CU0) & 0xf; -mx = (v >> CP0St_MX) & 0x1; -ksu = (v >> CP0St_KSU) & 0x3; -asid = env->CP0_EntryHi & 0xff; - -tcstatus = cu << CP0TCSt_TCU0; -tcstatus |= mx << CP0TCSt_TMX; -tcstatus |= ksu << CP0TCSt_TKSU; -tcstatus |= asid; - -if (tc == cpu->current_tc) { -tcst = >active_tc.CP0_TCStatus; -} else { -tcst = >tcs[tc].CP0_TCStatus; -} - -*tcst &= ~mask; -*tcst |= tcstatus; -compute_hflags(cpu); -} - -static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ -uint32_t mask = env->CP0_Status_rw_bitmask; -target_ulong old = env->CP0_Status; - -if (env->insn_flags & ISA_MIPS32R6) { -bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; -#if defined(TARGET_MIPS64) -uint32_t ksux = (1 << CP0St_KX) & val; -ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ -ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ -val = (val & ~(7 << CP0St_UX)) | ksux; -#endif -if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { -mask &= ~(3 << CP0St_KSU); -} -mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); -} - -env->CP0_Status = (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) -if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { -/* Access to at least one of the 64-bit segments has been disabled */ -cpu_mips_tlb_flush(env, 1); -} -#endif -if (env->CP0_Config3 & (1 << CP0C3_MT)) { -sync_c0_status(env, env, env->current_tc); -} else { -compute_hflags(env); -} -} - -static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ -uint32_t mask = 0x00C00300; -uint32_t old = env->CP0_Cause; -int i; - -if (env->insn_flags & ISA_MIPS32R2) { -mask |= 1 << CP0Ca_DC; -} -if (env->insn_flags & ISA_MIPS32R6) { -mask &= ~((1 << CP0Ca_WP) & val); -} - -env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); - -if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { -if (env->CP0_Cause & (1 << CP0Ca_DC)) { -cpu_mips_stop_count(env); -} else { -cpu_mips_start_count(env); -} -} - -/* Set/reset software interrupts */ -for (i = 0 ; i < 2 ; i++) { -if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { -cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); -} -} -} -#endif +void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global); +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, int error_code, uintptr_t pc); diff --git a/target-mips/helper.c b/target-mips/helper.c index 0fabfec..ac5771e 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -221,6 +221,114 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, } return ret; } + +void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global) +{ +MIPSCPU *cpu = mips_env_get_cpu(env); + +/* Flush qemu's TLB and discard all shadowed entries. */ +tlb_flush(CPU(cpu), flush_global); +env->tlb->tlb_in_use =
[Qemu-devel] [PATCH 45/50] mips: move CP0 functions out of cpu.h
These are here for historical reasons: they are needed from both gdbstub.c and op_helper.c, and the latter was compiled with fixed AREG0. It is not needed anymore, so uninline them. Signed-off-by: Paolo Bonzini--- target-mips/cpu.h| 113 ++- target-mips/helper.c | 108 2 files changed, 112 insertions(+), 109 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 0636327..951267a 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -1035,115 +1035,10 @@ static inline void compute_hflags(CPUMIPSState *env) } } -#ifndef CONFIG_USER_ONLY -static inline void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global) -{ -MIPSCPU *cpu = mips_env_get_cpu(env); - -/* Flush qemu's TLB and discard all shadowed entries. */ -tlb_flush(CPU(cpu), flush_global); -env->tlb->tlb_in_use = env->tlb->nb_tlb; -} - -/* Called for updates to CP0_Status. */ -static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ -int32_t tcstatus, *tcst; -uint32_t v = cpu->CP0_Status; -uint32_t cu, mx, asid, ksu; -uint32_t mask = ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - -cu = (v >> CP0St_CU0) & 0xf; -mx = (v >> CP0St_MX) & 0x1; -ksu = (v >> CP0St_KSU) & 0x3; -asid = env->CP0_EntryHi & 0xff; - -tcstatus = cu << CP0TCSt_TCU0; -tcstatus |= mx << CP0TCSt_TMX; -tcstatus |= ksu << CP0TCSt_TKSU; -tcstatus |= asid; - -if (tc == cpu->current_tc) { -tcst = >active_tc.CP0_TCStatus; -} else { -tcst = >tcs[tc].CP0_TCStatus; -} - -*tcst &= ~mask; -*tcst |= tcstatus; -compute_hflags(cpu); -} - -static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ -uint32_t mask = env->CP0_Status_rw_bitmask; -target_ulong old = env->CP0_Status; - -if (env->insn_flags & ISA_MIPS32R6) { -bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; -#if defined(TARGET_MIPS64) -uint32_t ksux = (1 << CP0St_KX) & val; -ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ -ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ -val = (val & ~(7 << CP0St_UX)) | ksux; -#endif -if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { -mask &= ~(3 << CP0St_KSU); -} -mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); -} - -env->CP0_Status = (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) -if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { -/* Access to at least one of the 64-bit segments has been disabled */ -cpu_mips_tlb_flush(env, 1); -} -#endif -if (env->CP0_Config3 & (1 << CP0C3_MT)) { -sync_c0_status(env, env, env->current_tc); -} else { -compute_hflags(env); -} -} - -static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ -uint32_t mask = 0x00C00300; -uint32_t old = env->CP0_Cause; -int i; - -if (env->insn_flags & ISA_MIPS32R2) { -mask |= 1 << CP0Ca_DC; -} -if (env->insn_flags & ISA_MIPS32R6) { -mask &= ~((1 << CP0Ca_WP) & val); -} - -env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); - -if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { -if (env->CP0_Cause & (1 << CP0Ca_DC)) { -cpu_mips_stop_count(env); -} else { -cpu_mips_start_count(env); -} -} - -/* Set/reset software interrupts */ -for (i = 0 ; i < 2 ; i++) { -if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { -cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); -} -} -} -#endif +void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global); +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, int error_code, uintptr_t pc); diff --git a/target-mips/helper.c b/target-mips/helper.c index 0fabfec..ac5771e 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -221,6 +221,114 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, } return ret; } + +void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global) +{ +MIPSCPU *cpu = mips_env_get_cpu(env); + +/* Flush qemu's TLB and discard all shadowed entries. */ +tlb_flush(CPU(cpu), flush_global); +env->tlb->tlb_in_use =