Re: [Qemu-devel] [PATCH 5/5] i.mx7d: pci: Update PCI IRQ mapping to match HW

[Peter Maydell]

On Tue, 16 Apr 2019 at 02:39, Andrey Smirnov  wrote:
>
> Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches
> that of i.MX6:
>
> * INTD/MSI122
> * INTC123
> * INTB124
> * INTA125
>
> Fix all of the relevant code to reflect that fact. Needed by latest
> Linux kernels.
>
> Signed-off-by: Andrey Smirnov 
> Cc: Peter Maydell 
> Cc: Michael S. Tsirkin 
> Cc: qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org
> ---
>  include/hw/arm/fsl-imx7.h | 8 
>  hw/pci-host/designware.c  | 6 --
>  2 files changed, 8 insertions(+), 6 deletions(-)

Reviewed-by: Peter Maydell 

Compare Linux kernel commit 538d6e9d597584e805146 from an
NXP employee confirming that the datasheet is incorrect
and with a report of a test against real h/w.

thanks
-- PMM

[Qemu-devel] [PATCH 5/5] i.mx7d: pci: Update PCI IRQ mapping to match HW

[Andrey Smirnov]

Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches
that of i.MX6:

* INTD/MSI122
* INTC123
* INTB124
* INTA125

Fix all of the relevant code to reflect that fact. Needed by latest
Linux kernels.

Signed-off-by: Andrey Smirnov 
Cc: Peter Maydell 
Cc: Michael S. Tsirkin 
Cc: qemu-devel@nongnu.org
Cc: qemu-...@nongnu.org
---
 include/hw/arm/fsl-imx7.h | 8 
 hw/pci-host/designware.c  | 6 --
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index 3efa697adc..9750003a4f 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -213,10 +213,10 @@ enum FslIMX7IRQs {
 FSL_IMX7_USB2_IRQ = 42,
 FSL_IMX7_USB3_IRQ = 40,
 
-FSL_IMX7_PCI_INTA_IRQ = 122,
-FSL_IMX7_PCI_INTB_IRQ = 123,
-FSL_IMX7_PCI_INTC_IRQ = 124,
-FSL_IMX7_PCI_INTD_IRQ = 125,
+FSL_IMX7_PCI_INTA_IRQ = 125,
+FSL_IMX7_PCI_INTB_IRQ = 124,
+FSL_IMX7_PCI_INTC_IRQ = 123,
+FSL_IMX7_PCI_INTD_IRQ = 122,
 
 FSL_IMX7_UART7_IRQ= 126,
 
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index e80facc4a0..f4c58b25c1 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -50,6 +50,8 @@
 #define DESIGNWARE_PCIE_ATU_DEVFN(x)   (((x) >> 16) & 0xff)
 #define DESIGNWARE_PCIE_ATU_UPPER_TARGET   0x91C
 
+#define DESIGNWARE_PCIE_IRQ_MSI3
+
 static DesignwarePCIEHost *
 designware_pcie_root_to_host(DesignwarePCIERoot *root)
 {
@@ -66,7 +68,7 @@ static void designware_pcie_root_msi_write(void *opaque, 
hwaddr addr,
 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
 
 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
-qemu_set_irq(host->pci.irqs[0], 1);
+qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);
 }
 }
 
@@ -310,7 +312,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, 
uint32_t address,
 case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
 root->msi.intr[0].status ^= val;
 if (!root->msi.intr[0].status) {
-qemu_set_irq(host->pci.irqs[0], 0);
+qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);
 }
 break;
 
-- 
2.20.1