Re: [Qemu-devel] [PATCH 5/9] target/arm: Implement FMOV (general) for fp16

[Richard Henderson]

On 04/24/2018 03:31 PM, Philippe Mathieu-Daudé wrote:
>> @@ -5431,10 +5446,15 @@ static void disas_fp_int_conv(DisasContext *s, 
>> uint32_t insn)
>>  case 0xa: /* 64 bit */
>>  case 0xd: /* 64 bit to top half of quad */
>>  break;
>> +case 0x6: /* 16-bit */
>> +if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
>> +break;
>> +}
>> +/* fallthru */
>>  default:
>>  /* all other sf/type/rmode combinations are invalid */
>>  unallocated_encoding(s);
>> -break;
>> +return;
> 
> Agreed with this change, however shouldn't this be in a separate patch?

Why?


r~

Re: [Qemu-devel] [PATCH 5/9] target/arm: Implement FMOV (general) for fp16

[Philippe Mathieu-Daudé]

Hi Richard,

On 04/24/2018 10:22 PM, Richard Henderson wrote:
> Adding the fp16 moves to/from general registers.
> 
> Signed-off-by: Richard Henderson 
> ---
>  target/arm/translate-a64.c | 22 +-
>  1 file changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index f2241d8174..36bb5f6f08 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -5375,6 +5375,15 @@ static void handle_fmov(DisasContext *s, int rd, int 
> rn, int type, bool itof)
>  tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
>  clear_vec_high(s, true, rd);
>  break;
> +case 3:
> +/* 16 bit */
> +tmp = tcg_temp_new_i64();
> +tcg_gen_ext16u_i64(tmp, tcg_rn);
> +write_fp_dreg(s, rd, tmp);
> +tcg_temp_free_i64(tmp);
> +break;
> +default:
> +g_assert_not_reached();
>  }
>  } else {
>  TCGv_i64 tcg_rd = cpu_reg(s, rd);
> @@ -5392,6 +5401,12 @@ static void handle_fmov(DisasContext *s, int rd, int 
> rn, int type, bool itof)
>  /* 64 bits from top half */
>  tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
>  break;
> +case 3:
> +/* 16 bit */
> +tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
> +break;
> +default:
> +g_assert_not_reached();
>  }
>  }
>  }
> @@ -5431,10 +5446,15 @@ static void disas_fp_int_conv(DisasContext *s, 
> uint32_t insn)
>  case 0xa: /* 64 bit */
>  case 0xd: /* 64 bit to top half of quad */
>  break;
> +case 0x6: /* 16-bit */
> +if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
> +break;
> +}
> +/* fallthru */
>  default:
>  /* all other sf/type/rmode combinations are invalid */
>  unallocated_encoding(s);
> -break;
> +return;

Agreed with this change, however shouldn't this be in a separate patch?

>  }
>  
>  if (!fp_access_check(s)) {
> 

[Qemu-devel] [PATCH 5/9] target/arm: Implement FMOV (general) for fp16

[Richard Henderson]

Adding the fp16 moves to/from general registers.

Signed-off-by: Richard Henderson 
---
 target/arm/translate-a64.c | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index f2241d8174..36bb5f6f08 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5375,6 +5375,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, 
int type, bool itof)
 tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
 clear_vec_high(s, true, rd);
 break;
+case 3:
+/* 16 bit */
+tmp = tcg_temp_new_i64();
+tcg_gen_ext16u_i64(tmp, tcg_rn);
+write_fp_dreg(s, rd, tmp);
+tcg_temp_free_i64(tmp);
+break;
+default:
+g_assert_not_reached();
 }
 } else {
 TCGv_i64 tcg_rd = cpu_reg(s, rd);
@@ -5392,6 +5401,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn, 
int type, bool itof)
 /* 64 bits from top half */
 tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
 break;
+case 3:
+/* 16 bit */
+tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
+break;
+default:
+g_assert_not_reached();
 }
 }
 }
@@ -5431,10 +5446,15 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t 
insn)
 case 0xa: /* 64 bit */
 case 0xd: /* 64 bit to top half of quad */
 break;
+case 0x6: /* 16-bit */
+if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+break;
+}
+/* fallthru */
 default:
 /* all other sf/type/rmode combinations are invalid */
 unallocated_encoding(s);
-break;
+return;
 }
 
 if (!fp_access_check(s)) {
-- 
2.14.3