Re: [Qemu-devel] [PATCH 8/9] adding instruction translations

[Michael Rolnik]

right. no reason. I can make it just a C file.
when I started I was not sure what was the best way to do it as I generate
some come code.
thanks, I will fix it.

On Thu, Jun 2, 2016 at 9:44 AM, Richard Henderson  wrote:

> On 05/29/2016 06:23 PM, Michael Rolnik wrote:
>
>> Signed-off-by: Michael Rolnik 
>> ---
>>  target-avr/translate.c.inc | 2546
>> 
>>  1 file changed, 2546 insertions(+)
>>  create mode 100644 target-avr/translate.c.inc
>>
>
> Is there any good reason for you to pull out these functions into an
> include file?  I think this is simply confusing.
>
>
> r~
>



-- 
Best Regards,
Michael Rolnik

Re: [Qemu-devel] [PATCH 8/9] adding instruction translations

[Richard Henderson]

On 05/29/2016 06:23 PM, Michael Rolnik wrote:

Signed-off-by: Michael Rolnik 
---
 target-avr/translate.c.inc | 2546 
 1 file changed, 2546 insertions(+)
 create mode 100644 target-avr/translate.c.inc


Is there any good reason for you to pull out these functions into an include 
file?  I think this is simply confusing.



r~

[Qemu-devel] [PATCH 8/9] adding instruction translations

[Michael Rolnik]

Signed-off-by: Michael Rolnik 
---
 target-avr/translate.c.inc | 2546 
 1 file changed, 2546 insertions(+)
 create mode 100644 target-avr/translate.c.inc

diff --git a/target-avr/translate.c.inc b/target-avr/translate.c.inc
new file mode 100644
index 000..74b3c2c
--- /dev/null
+++ b/target-avr/translate.c.inc
@@ -0,0 +1,2546 @@
+/*
+ *  QEMU AVR CPU
+ *
+ *  Copyright (c) 2016 Michael Rolnik
+ *
+ *  This library is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU Lesser General Public
+ *  License as published by the Free Software Foundation; either
+ *  version 2.1 of the License, or (at your option) any later version.
+ *
+ *  This library is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  Lesser General Public License for more details.
+ *
+ *  You should have received a copy of the GNU Lesser General Public
+ *  License along with this library; if not, see
+ *  
+ */
+
+#include 
+#include 
+
+#ifdef  HOST_WORDS_BIGENDIAN
+#include "inst-be.h"
+#else
+#include "inst-le.h"
+#endif
+
+/*
+NOTE:   all registers are assumed to hold 8 bit values.
+so all operations done on registers should preseve this property
+*/
+
+/*
+NOTE:   the flags C,H,V,N,V have either 0 or 1 values
+NOTE:   the flag Z has inverse logic, when the value of Zf is 0 the flag 
is assumed to be set, non zero - not set
+*/
+
+voidgen_add_CHf(TCGvR, TCGvRd, TCGvRr);
+voidgen_add_Vf( TCGvR, TCGvRd, TCGvRr);
+voidgen_sub_CHf(TCGvR, TCGvRd, TCGvRr);
+voidgen_sub_Vf( TCGvR, TCGvRd, TCGvRr);
+voidgen_ZNSf(   TCGvR);
+voidgen_push_ret(   CPUAVRState *env, intret);
+voidgen_pop_ret(CPUAVRState *env, TCGvret);
+voidgen_jmp_ez( void);
+voidgen_jmp_z(  void);
+
+voidgen_set_addr(   TCGv addr, TCGv H, TCGv M, TCGv l); /*  H:M:L   = addr 
 */
+voidgen_set_xaddr(  TCGv addr);
+voidgen_set_yaddr(  TCGv addr);
+voidgen_set_zaddr(  TCGv addr);
+
+TCGvgen_get_addr(   TCGv H, TCGv M, TCGv L);/*  addr = H:M:L   
 */
+TCGvgen_get_xaddr(  void);
+TCGvgen_get_yaddr(  void);
+TCGvgen_get_zaddr(  void);
+int sex(int Imm, unsigned bits);
+
+voidgen_add_CHf(TCGvR, TCGvRd, TCGvRr)
+{
+TCGvt1  = tcg_temp_new_i32();
+TCGvt2  = tcg_temp_new_i32();
+TCGvt3  = tcg_temp_new_i32();
+
+tcg_gen_and_tl( t1, Rd, Rr);/*  t1  = Rd & Rr  */
+tcg_gen_not_tl( t2, R); /*  t2  = Rd & ~R  */
+tcg_gen_and_tl( t2, Rd, t2);
+tcg_gen_not_tl( t3, R); /*  t3  = Rr  *~R  */
+tcg_gen_and_tl( t3, Rr, t3);
+tcg_gen_or_tl(  t1, t1, t2);/*  t1  = t1 | t2 | t3  */
+tcg_gen_or_tl(  t1, t1, t3);
+
+tcg_gen_shri_tl(cpu_Cf, t1, 7); /*  Cf  = t1(7)  */
+tcg_gen_shri_tl(cpu_Hf, t1, 3); /*  Hf  = t1(3)  */
+tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+
+tcg_temp_free_i32(t3);
+tcg_temp_free_i32(t2);
+tcg_temp_free_i32(t1);
+}
+
+voidgen_add_Vf(TCGvR, TCGvRd, TCGvRr)
+{
+TCGvt1  = tcg_temp_new_i32();
+TCGvt2  = tcg_temp_new_i32();
+
+tcg_gen_not_tl( t1, Rd);/*  t1  = ~Rd & ~Rr & R  */
+tcg_gen_not_tl( t2, Rr);
+tcg_gen_and_tl( t1, t1, t2);
+tcg_gen_and_tl( t1, t1, R);
+
+tcg_gen_not_tl( t2, R); /*  t2  = Rd & Rr & ~R  */
+tcg_gen_and_tl( t2, t2, Rd);
+tcg_gen_and_tl( t2, t2, Rr);
+
+tcg_gen_or_tl(  t1, t1, t2);/*  t1  = Rd & Rr & ~R | ~Rd & ~Rr 
& R  */
+
+tcg_gen_shri_tl(cpu_Vf, t1, 7); /*  Vf  = t1(7)  */
+
+tcg_temp_free_i32(t2);
+tcg_temp_free_i32(t1);
+}
+
+voidgen_sub_CHf(TCGvR, TCGvRd, TCGvRr)
+{
+TCGvt1  = tcg_temp_new_i32();
+TCGvt2  = tcg_temp_new_i32();
+TCGvt3  = tcg_temp_new_i32();
+
+/*  Cf & Hf  */
+tcg_gen_not_tl( t1, Rd);/*  t1  = ~Rd  */
+tcg_gen_and_tl( t2, t1, Rr);/*  t2  = ~Rd & Rr  */
+tcg_gen_or_tl(  t3, t1, Rr);/*  t3  = (~Rd | Rr) & R  */
+tcg_gen_and_tl( t3, t3, R);
+tcg_gen_or_tl(  t2, t2, t3);/*  t2  = ~Rd & Rr | ~Rd & R | R & 
Rr  */
+tcg_gen_shri_tl(cpu_Cf, t2, 7); /*  Cf  = t2(7)  */
+tcg_gen_shri_tl(cpu_Hf, t2, 3); /*  Hf  = t2(3)  */
+tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+
+tcg_temp_free_i32(t3);
+tcg_temp_free_i32(t2);
+tcg_temp_free_i32(t1);
+}
+
+voidgen_sub_Vf(TCGvR, TCGvRd, TCGvRr)
+{
+TCGvt1  = tcg_temp_new_i32();
+TCGv